Is it necessary to turn an ADC off between conversions ? and how ?

Thread Starter

Matt74

Joined Jun 29, 2019
30
Hi all,

I would like a small and simple fuel gauge for a coin cell operated device. I am trying to minimise power consumption as much as possible. I thought the ADS7040 would be ideal but I am wondering whether I should use a load switch to turn it off because I am only going to read battery voltage once every 2 min at most. The SiP32431 for instance has a nA range quiescent current, difficult to beat !
I guess the ADC is meant to be used continuously because I can't find on the datasheet the power consumption when it's off...

Second question: What would be the best way to turn it off ? Stop the clock ? Connect DVDD to a GPIO and turn it low ? Both ? None of the above ?

Thanks !

Datasheets:
https://www.ti.com/lit/ds/symlink/ads7040.pdf?ts=1619617854706&ref_url=https%3A%2F%2Fwww.ti.com%2Fproduct%2FADS7040
https://www.vishay.com/docs/66597/sip32431.pdf

PS: I am not posting any schematics because it is a conceptual question
 

Papabravo

Joined Feb 24, 2006
16,777
Conceptually, the answer to your requires a knowledge of the entire system. For example if you have a processor with a lower performance A/D converter, that can be powered off your overall performance may be better. Refer to section 10.3 for optimizing power consumption. If you can run at 1.8 Volts that looks like it might be the ticket. Interestingly running conversion continuously is supposed to be better than occasional. I don't know why that would be the case, but a TI FAE might know the answer. If you can find one that is.
 

Ian0

Joined Aug 7, 2020
3,221
From the datasheet, it appears as though the power is proportional to the sample rate, and it samples when CS goes low. My guess is that if you don’t read it, it doesn’t sample and the power consumption would be as low as it could be.
. . . But that’s rather “reading between the lines“ of the datasheet.
 

nsaspook

Joined Aug 27, 2009
8,660
The device is clocked from the SPI interface. With no commands for a ADC conversion it only uses the quiescent DC current so power saving is automatic until you start to trigger conversions with SPI commands.
8.3.4 Serial Interface
The device supports a simple, SPI-compatible interface to the external host. The CS signal defines one
conversion and serial transfer frame. A frame starts with a CS falling edge and ends with a CS rising edge. The
SDO pin outputs the ADC conversion results. Figure 35 shows a detailed timing diagram for the serial interface.
A minimum delay of tSU_CSCK must elapse between the CS falling edge and the first SCLK falling edge. The
device uses the clock provided on the SCLK pin for conversion and data transfer. The conversion result is
available on the SDO pin with the first two bits set to 0, followed by 8 bits of the conversion result. The first zero
is launched on the SDO pin on the CS falling edge. Subsequent bits (starting with another 0 followed by the
conversion result) are launched on the SDO pin on subsequent SCLK falling edges. The SDO output remains
low after 10 SCLKs. A CS rising edge ends the frame and brings the serial data bus to 3-state. For acquisition of
the next sample, a minimum time of tACQ must be provided after the conversion of the current sample is
completed. For details on timing specifications, see the Timing Characteristics table.
The device initiates an offset calibration on the first CS falling edge after power-up and the SDO output remains
low during the first serial transfer frame after power-up. For further details, refer to the Offset Calibration section.
 

Thread Starter

Matt74

Joined Jun 29, 2019
30
Thanks for your answers.
More details : I am running at 2.7V and I don't have any native A/D on the processor hence the need for an external one.

I guess my question was: is the "quiescent DC current" / "as low as it could be" current significantly higher than the 0.01-100nA used by the switch when off.
Yes it does take a lot of "reading between the lines", which I was struggling with and for which I asked for help ;)
Thx
 

Yaakov

Joined Jan 27, 2019
3,483
Thanks for your answers.
More details : I am running at 2.7V and I don't have any native A/D on the processor hence the need for an external one.

I guess my question was: is the "quiescent DC current" / "as low as it could be" current significantly higher than the 0.01-100nA used by the switch when off.
Yes it does take a lot of "reading between the lines", which I was struggling with and for which I asked for help ;)
Thx
You may have a more difficult problem than power consumption if you are trying to determine SoC from the battery voltage.
 

cmartinez

Joined Jan 17, 2007
7,393
I recently worked on a project that required sporadic ADC readings, but extremely low power draw was also a requisite. I discovered that even changing the settings in the device to make it ready for ADC readings significantly affected it and jumped from consuming a few microamps to several milliamps.

What I did was monitor the device's power draw when each and every instruction was executed, and wrote a couple if routines that would enable and disable said features on demand.
 
Last edited:

nsaspook

Joined Aug 27, 2009
8,660
Thanks for your answers.
More details : I am running at 2.7V and I don't have any native A/D on the processor hence the need for an external one.

I guess my question was: is the "quiescent DC current" / "as low as it could be" current significantly higher than the 0.01-100nA used by the switch when off.
Yes it does take a lot of "reading between the lines", which I was struggling with and for which I asked for help ;)
Thx
Without knowing exactly what your battery life and total processing current budget is it's hard to know if the extra current draw savings from a switch will make a significant difference over the cell lifetime. Every ADC power up cycle is going to require extra run-time and CPU power to initialize and calibrate the ADC.
 

BobTPH

Joined Jun 5, 2013
3,655
I don’t know what you are asking for. You talk about turning it off by removing power. If it is not piwered, the power usage is zero. And the quiescent current tells you how much power it uses when powered, but not doing a conversion. So what other number are you looking for?

Bob
 

Thread Starter

Matt74

Joined Jun 29, 2019
30
I don’t know what you are asking for. You talk about turning it off by removing power. If it is not piwered, the power usage is zero. And the quiescent current tells you how much power it uses when powered, but not doing a conversion. So what other number are you looking for?

Bob
Excellent point bob. If the ADC data sheet was indicating the quiescent current I would have my answer and I would't have posted the question here. Unless I missed it (possible) it is not clearly stated.
 

BobTPH

Joined Jun 5, 2013
3,655
OIK, now I understand. Actually you can compute it from the data given.

We have the avg current at 1M and 100K samples per second, each of which is the sum of the quiescent current and the current used when sampling. This gives you two equations in two variables.

185 = q + 1e6 x
23 = q + 1e5 x

Where q is the quiescent current and x is the contribution of 1 sample per second to the avg current.

Solving for q I get 5 uA.

Bob
 

Thread Starter

Matt74

Joined Jun 29, 2019
30
OIK, now I understand. Actually you can compute it from the data given.

We have the avg current at 1M and 100K samples per second, each of which is the sum of the quiescent current and the current used when sampling. This gives you two equations in two variables.

185 = q + 1e6 x
23 = q + 1e5 x

Where q is the quiescent current and x is the contribution of 1 sample per second to the avg current.

Solving for q I get 5 uA.

Bob
Perfect :)
So that’s still several order of magnitude higher than the switch quiescent current so even taking into account the unavoidable consumption peak when the ADC turns on, It sounds like the switch is the way to go. I’ll keep in mind cmartinez’s suggestion about code optimisation.
Cheers guys !
 

cmartinez

Joined Jan 17, 2007
7,393
Perfect :)
So that’s still several order of magnitude higher than the switch quiescent current so even taking into account the unavoidable consumption peak when the ADC turns on, It sounds like the switch is the way to go. I’ll keep in mind cmartinez’s suggestion about code optimisation.
Cheers guys !
I suggest you start by making the MCU execute nothing but an empty loop. Then check if the lowest power draw promised by the datasheet is indeed the case. If not, tweak its default settings (oscillator, the state of its inputs and outputs, etc) until that point is reached.

After that, measure its power draw every time you add a routine. That way you will know exactly which settings affect its performance and will also let you structure the firmware in the most efficient and comprehensive way.
 

kubeek

Joined Sep 20, 2005
5,757
What a lousy datasheet. In chapter 8, Device functional modes there is alot of words about calibration, but not a single word about actual measuring-functioning use case.

Then they say in marketing wank that it is "Ultra low power", cool, but on the other hand they specify the typical supply current only at 1Msps and 100ksps, but the minimum TIMING REQUIREMENT for SPI clock frequency on page 7 is 16kHz. How much current does it consume at 16kHz? How much current does it consume at 0Hz? What happens if I use just 1kHz, does it measure garbage?
And if my spi clock is lower than that 16kHz by many orders of magnitude, i.e no clock pulse for a month, am I using the chip outside the allowed parameters and should not trust it anymore after that event?
 

Ian0

Joined Aug 7, 2020
3,221
What a lousy datasheet.
You know what they say about a bad workman . . . . .
but not a single word about actual measuring-functioning use case.
. .. apart from the whole of section 9.2 which gives you the input circuit and the anti-aliasing filter, and section 6.6 which gives you the timing of the SPI interface.
Are we both reading the same datasheet?
And if my spi clock is lower than that 16kHz by many orders of magnitude, i.e no clock pulse for a month,
As it's a successive approximation register type of A/D, there will be some internal sample-and-hold, for which 16kHz clock (i.e. 625us) represents the maximum hold time of the capacitor. It will operate right down to zero but if the sample and hold cannot hold for that length of time, your data might be nonsense.
How much current does it consume at 16kHz?
See the graph in figures 27 and 28.
How much current does it consume at 0Hz?
That's in the graph in figures 27/28 as well.
am I using the chip outside the allowed parameters and should not trust it anymore after that event?
No - if you were, it would be in section 6.1 "Absolute maximum ratings"
 

kubeek

Joined Sep 20, 2005
5,757
. .. apart from the whole of section 9.2 which gives you the input circuit and the anti-aliasing filter, and section 6.6 which gives you the timing of the SPI interface.
Are we both reading the same datasheet?
I don´t know, maybe I am a bit too picky, but the chapter 9 is called function modes, and I would expect 9.1 to be called "normal operation". Then it would show Reset state in a fancy diagram going to first aquisition state, where it should say that after powerup I should use the same timing from chapter 6.6, but the first result will be maybe random, maybe zeroes, maybe my phone number, but no conversion will happen until I do this first read and that this first read is what actually makes the conversion. I would expect there to be a remark that the timing of the clock for that read directly influences the conversion process, and if my timing is as sloppy as bit banging on an arduino, then the precision of the conversion will be just as sloppy.
As it's a successive approximation register type of A/D, there will be some internal sample-and-hold, for which 16kHz clock (i.e. 625us) represents the maximum hold time of the capacitor. It will operate right down to zero but if the sample and hold cannot hold for that length of time, your data might be nonsense.
Again, a lot of implied knowledge, which should either be mentioned, or there should be a link to a general application note for SAR converters that covers that caveat.
the graph in figures 27 and 28.
That line is thick as hell, and doesn´t even touch the 0Hz line and 16khz is nowhere to be seen. Can you tell me what that 0Hz number is? My point being if they boast nanowatt consumption, all figures are i microwatts, and there is no mention of quiescent current, how do I know if I need to turn the power for the ADC off or not when I am using it in a truly power sensitive application?
 
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