Hi, I want to know why are not equal the rise times of output pulse in inverter

 

Welcome to AAC!

Any particular inverter? Loaded or unloaded?

 

Yes any particular inverter.Loaded with 10f cap

 

Yes any particular inverter.

Some inverters will have asymmetrical rise/fall times, but most will be symmetrical. You need to give a part number.

Loaded with 10f cap

Do you really mean 10F? That's a huge capacitance for an inverter to drive.

 

I said, for example 10f,but I want to know the physics why are not equal the rise times...I think this effect connected with the change of input capacitance pmos transistor...I take 32nm transistors from SAED library

 

I want to know the physics why are not equal the rise times...I think this effect connected with the change of input capacitance pmos transistor...I take 32nm transistors from SAED library

It's more related to the relative drive strengths of the PMOS and NMOS transistor. In older process technologies, NMOS drive was 1.5-2X that of PMOS, so PMOS devices were made larger to compensate for that. In later process generations, drive strength became more equal. I can't recall when the transition took place, but it depends on the process technology; and each company has different recipes.

You should be able to look up drive strengths in the process file.

 

Tank you for help