I'm trying to use LMX04832 with external VCO with Si569 being the VCO. Chose CML as I think it to be optimal in terms of speed and power consumption. So, there is the trick. The LMX04832 datasheet provides no explicit data on interfacing between its clock input and a CML output stage. It seems like Si569 will not tolerate any external DC path between its outputs (see attachment), so they recommend placing a termination resistor after DC blocking caps. LMX04832 "wants" the opposite: termination before the DC block (the other attachment), which is understandable because the clock input is DC biased internally.

So, how do I actually interface these devices?

At the moment, it seems like CML may work if I use the same configuration as suggested by TI datasheet for LVPECL but without the emitter resistors (since they are not required by a CML output stage). The trace length will not exceed approx. 10mm. I will also try to simulate this and post the results later on.

 

Can you expand on why you have chosen CML.
Are you at Ghz ?
If not, LVDS is more than capable up to GHz frequency's , is supported by both chips and is low noise / low power.

 

Can you expand on why you have chosen CML.
Are you at Ghz ?
If not, LVDS is more than capable up to GHz frequency's , is supported by both chips and is low noise / low power.

Yeah, up to 2 GHz is required. The datasheet of Si569 claims that it is capable of up to 3 GHz with LVDS output stage as well, but I am not aware of LVDS being able to yield more than ~800 MHz. So I took some precautions.