I've posted truth table above. Here it comes again>View attachment 114350

You should describe, briefly, what your truth tables are for. Don't make people guess, because that will lead to subtle miscommunications that can be hard to even detect.

I'm assuming (because I am having to guess) that the left table is telling you that if the current output is the value in the Q column and you want the Q to have the value in the Q(t+1) column after the next rising clock edge, that the values of R and S need to be those given on the same line and that 'b' means that both values are acceptable. In most places this is known as a "don't care" condition and the letter 'x' is used, but use whatever your text/teacher uses and just be sure that you let people know what it means.

I'm assuming (again, having to guess) that the right table is telling me what happens to Q after the next rising clock edge given the values of the R and S inputs. Here the 'b' is more ambiguous because it's impossible to have "both" values. I think you mean that the value is unknown (though in most RSFF implementations the behavior is actually well defined -- but it is an input condition that is discouraged), in which case using '?' or 'x' is more common (in most places).

You still have this en0 input in your RSFF symbols. Is this really there? If so, what is the behavior when this is 0 and when it is 1?

While having the Truth Table (or other descriptive behavior) for the RSFF is important, it is not everything. You also need to clearly define, via Truth Table or other means, how the overall system is supposed to behave in response to all of its inputs. You finally stated (in Post #7) that C0 indicated that it should count up and that E0 indicates if it should count down. First off, how are these indicated? Does C0 indicate to count up if it is HI, or if it is LO. The signal name is meaningless in terms of implying signal polarity. Second, there are four possible combinations of the values of C0 and E0. What should happen if both are HI? If both are LO?

You also indicated that this is supposed to be asynchronous. That implies that there is no clock. This probably also means that the Co and Eo signals are strobed (e.g., a LO-HI-LO pulse on the Co line causes the counter to increment by 1). But there are several possible specifications and it is hard to help you unless you make it clear what the specifications are that you are designing to.

 

The first diagram was a suitable topology. All you had to do was substitute the SR flip flop and make the increment and decrement two circuits.

 

You should describe, briefly, what your truth tables are for. Don't make people guess, because that will lead to subtle miscommunications that can be hard to even detect.

I'm assuming (because I am having to guess) that the left table is telling you that if the current output is the value in the Q column and you want the Q to have the value in the Q(t+1) column after the next rising clock edge, that the values of R and S need to be those given on the same line and that 'b' means that both values are acceptable. In most places this is known as a "don't care" condition and the letter 'x' is used, but use whatever your text/teacher uses and just be sure that you let people know what it means.

I'm assuming (again, having to guess) that the right table is telling me what happens to Q after the next rising clock edge given the values of the R and S inputs. Here the 'b' is more ambiguous because it's impossible to have "both" values. I think you mean that the value is unknown (though in most RSFF implementations the behavior is actually well defined -- but it is an input condition that is discouraged), in which case using '?' or 'x' is more common (in most places).

You still have this en0 input in your RSFF symbols. Is this really there? If so, what is the behavior when this is 0 and when it is 1?

While having the Truth Table (or other descriptive behavior) for the RSFF is important, it is not everything. You also need to clearly define, via Truth Table or other means, how the overall system is supposed to behave in response to all of its inputs. You finally stated (in Post #7) that C0 indicated that it should count up and that E0 indicates if it should count down. First off, how are these indicated? Does C0 indicate to count up if it is HI, or if it is LO. The signal name is meaningless in terms of implying signal polarity. Second, there are four possible combinations of the values of C0 and E0. What should happen if both are HI? If both are LO?

You also indicated that this is supposed to be asynchronous. That implies that there is no clock. This probably also means that the Co and Eo signals are strobed (e.g., a LO-HI-LO pulse on the Co line causes the counter to increment by 1). But there are several possible specifications and it is hard to help you unless you make it clear what the specifications are that you are designing to.

This was actually quite helpful. But I first have to find and read in English all the materials that I've studied from, and that might take time. In order to figure out how to ask the right questions. Up until now I didn't understand how different circuit-talk can be just because of the native language. . .
I apologize for not being precise enough. Tnx & I'm glad to have stumbled upon this forum

 

Here's an example of a Mod 12 up/down counter using D FF.

First few rows:


Complete table attached.

 

Finally, I can say that I got it!
Thanks to everyone who tried to help
Here is my solution to given problem, for anyone whom might have same issue:

 

Hopefully it works (and hopefully you understand how it works, since it has the odor of something that you found or was given to you instead of something you designed since you've given no evidence of any design effort).

We can't tell if it does or not because you never did provide a complete spec of how it is supposed to work. You were asked to describe how the circuit was supposed to behave when neither C0 or E0 were asserted and also when they were both asserted. You never did. Also, what you did provide is not consistent with your solution. You provided a truth table for an RSFF that did not have this en0 input and you have yet to indicate how the RSFF is supposed to behave in response to this input even though you were specifically asked.

 

Hopefully it works (and hopefully you understand how it works, since it has the odor of something that you found or was given to you instead of something you designed since you've given no evidence of any design effort).

We can't tell if it does or not because you never did provide a complete spec of how it is supposed to work. You were asked to describe how the circuit was supposed to behave when neither C0 or E0 were asserted and also when they were both asserted. You never did. Also, what you did provide is not consistent with your solution. You provided a truth table for an RSFF that did not have this en0 input and you have yet to indicate how the RSFF is supposed to behave in response to this input even though you were specifically asked.

I didn't ask correct questions, neither did I give correct information, because of lack of knowledge on given subject.
I will post truth tables and how it is supposed to work. I did indicate that C0=E0=1 is a forbidden state.
This must be irritating, but I am sorry for wasting your time with misinformation...

[This is for those who can read my native, and have same issue]>

Realizovati kao jedinstvenu sekvencijalnu mrežu inkrementirajuće/dekrementirajući brojač po modulu 16 sa RS flip flopovima sa kaskadnim generisanjem signala prenosa. Upravljački signali su Co i Eo (Co = Eo = 1 je zabranjena kombinacija upravljačkih signala).​

 

Implement as a single sequential network incrementing / dekrementirajući counter modulo 16 with RS flip flopovima cascade generating signal transmission. Control signals are Co and Eo (Co = Eo = 1 is prohibited combination of control signals).

That is not what you said in your opening post.

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Implement as a single sequential network incrementing / dekrementirajući counter modulo 16 with RS flip flopovima cascade generating signal transmission. Control signals are Co and Eo (Co = Eo = 1 is prohibited combination of control signals).

That is not what you said in your opening post.

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I'm now left wondering did you write a bot for this forum to auto-translate, or you wanted to make some point?

 

Your first topology was perfectly good. Your solution above allows Co and Eo to equal one.

 

Your first topology was perfectly good. Your solution above allows Co and Eo to equal one.

I know, but my first topology was returned to me as wrong, and this one gave me credits. That is why I was so confused.
I even pointed my teaching assistant to this forum, which he considered as cheating...

 

I didn't write anything, I used Google translate. It translated enough to grasp the problem you were attempting to solve.

 

I didn't ask correct questions, neither did I give correct information, because of lack of knowledge on given subject.
I will post truth tables and how it is supposed to work. I did indicate that C0=E0=1 is a forbidden state.
This must be irritating, but I am sorry for wasting your time with misinformation...

[This is for those who can read my native, and have same issue]>

Realizovati kao jedinstvenu sekvencijalnu mrežu inkrementirajuće/dekrementirajući brojač po modulu 16 sa RS flip flopovima sa kaskadnim generisanjem signala prenosa. Upravljački signali su Co i Eo (Co = Eo = 1 je zabranjena kombinacija upravljačkih signala).​

I missed where you said that C0=E0=1 was forbidden. I'm then assuming that C0=E0=0 means hold the current count.

It's not that it is a waste of my time (if I felt that way I would simply not respond), but rather that YOU can benefit from being held to an expectation of providing sufficiently clear and complete information -- and, yes, I definitely understand that English as a second language makes that harder (and, believe me, your English is FAR better than my Serbian (or whatever the correct name for your native tongue is)).

 

I know, but my first topology was returned to me as wrong, and this one gave me credits. That is why I was so confused.
I even pointed my teaching assistant to this forum, which he considered as cheating...

Depending on the expectation for the assignment, using this forum in any way may well be cheating. However, it might not be. We don't know and that is something that is between you and your instructor -- the best way to deal with that is to ask, up front, whether the use of resources such as this are acceptable and, if so, what restrictions you need to abide by.

 

I missed where you said that C0=E0=1 was forbidden. I'm then assuming that C0=E0=0 means hold the current count.

It's not that it is a waste of my time (if I felt that way I would simply not respond), but rather that YOU can benefit from being held to an expectation of providing sufficiently clear and complete information -- and, yes, I definitely understand that English as a second language makes that harder (and, believe me, your English is FAR better than my Serbian (or whatever the correct name for your native tongue is)).

Yep, Serbian.
Well, I love being punctual, exact, but in this situation I wasn't able to. That pisses me off. Plus, assistant gave me some extra confusion, and that almost pushed me to give up. Luckily I didn't. Now I can do another part of the subject, which is 4 bit register using JKff in VHDL in Xilinx software.
Do people on this forum help with those things as well? Should I start a separate thread?

 

Depending on the expectation for the assignment, using this forum in any way may well be cheating. However, it might not be. We don't know and that is something that is between you and your instructor -- the best way to deal with that is to ask, up front, whether the use of resources such as this are acceptable and, if so, what restrictions you need to abide by.

The trouble is that he wasn't aware that such forum existed. Now, I bet, he can't sleep! XD

 

Yep, Serbian.
Well, I love being punctual, exact, but in this situation I wasn't able to. That pisses me off. Plus, assistant gave me some extra confusion, and that almost pushed me to give up. Luckily I didn't. Now I can do another part of the subject, which is 4 bit register using JKff in VHDL in Xilinx software.
Do people on this forum help with those things as well? Should I start a separate thread?

Yes, people help with that stuff as well.

Yes, you should start a separate thread.

The general rule is one problem per thread -- otherwise it gets extremely confusing because readers can't keep straight which post is in response to which problem.

 

The trouble is that he wasn't aware that such forum existed. Now, I bet, he can't sleep! XD

Their point will likely be that it doesn't matter whether they were aware of a resource or not. Remember, the purpose of an assignment is for YOU to demonstration YOUR knowledge of the material. So if YOU want to use ANY resource that they have not explicitly indicated as allowable, then the burden is on YOU to establish that it IS okay to use it BEFORE you use it.

 

Their point will likely be that it doesn't matter whether they were aware of a resource or not. Remember, the purpose of an assignment is for YOU to demonstration YOUR knowledge of the material. So if YOU want to use ANY resource that they have not explicitly indicated as allowable, then the burden is on YOU to establish that it IS okay to use it BEFORE you use it.

I totally agree. I do honor the code of conduct, to the letter. Only, professors and teaching assistants have no understanding if we use any material that didn't come from them -- Third World teaching issues. )

And again, thanks everyone for help.

 

We fully understand your professor's concern. Hopefully he or his assistants join these forums, and there are quite a few, to see how we operate, specifically acting in a guiding manner and not just giving you the answer to the problem. Granted, now and then, someone puts the answer in a thread, but they are reminded that it does the thread starter no good if you answer the assignment for them.

You were upset earlier, and it was quite easy just quit on you ... but you see that WBahn stayed engaged with you with respect to this problem.

I'm glad you got some points.

I think the google translator worked pretty well ... it does well with Greco-Roman languages. Some of the others have unusual translations.