Improving rising and falling time of AD8561

Thread Starter

m.serdar

Joined Sep 23, 2016
3
Hello. I tried a basic circuit with AD8561 comparator. The circuits and the output is under this post. I wonder that if this 800us rising and falling time can be reduce or not. Thanks in advance!yükselme zamanında gecikme.jpg
 

crutschow

Joined Mar 14, 2008
38,584
Your simulation appears to be way off.
Even with such a slow input slew rate, the output rise/fall times should be well below 100μs.
Try reducing the Maximum Timestep to 100ns.
Also try a higher input frequency (such as 100kHz) and see if that makes a difference.
 

ci139

Joined Jul 11, 2016
2,008
what are you exactly measuring on your schematic o_O
? the scope ports (ups! - sorry now i see it G CH1 CH2)
LT Spice ↓↓↓ "thinks"
_Draft-AD-comp-E00.png
(((? the digital ground -- pin 6 - is not specified in datasheet -- must dig it out from the web . . . digging . . . seems smth I/O signal chains unbound de-couple ? with common Vcc . . . am i loosing it ??? ))))
http://www.analog.com/media/en/technical-documentation/application-notes/AN-352.pdf
i gess that defines it ? referencing your input to digital ground ? further chk-s . . .
http://www.analog.com/media/en/technical-documentation/data-sheets/AD790.pdf
i don't have "data hold" or "latch" working in simulation ... yet
 
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Thread Starter

m.serdar

Joined Sep 23, 2016
3
I will use it as square wave generator from the output of amplified emg signal...Amplified emg signal peak value is 5 volt and about max. 500Hz...and the referans voltage is 1.7 volt. So if the amplified emg signal is bigger than the referans the output will be 5v..and the other condition it will be zero...I want perfect square so i wonder if i can improve the rising or falling time...
 

ci139

Joined Jul 11, 2016
2,008
Google Images [comparator input transformer]
http://www.ko4bb.com/Timing/ClockShaper.php
http://electronics.stackexchange.com/questions/47255/sct-sensor-to-0-10v-analog-input
((http://www.analog.com/library/analogdialogue/archives/49-04/input_protection.html))
filter (in the mind) = similar apps , related materials (that might be useful by their context)

LT1016 - shows the digital ground to be the output ground - either the AD model is not fully integral - or - they define/implement it differently ??? running spice compare ...
_Draft-AD-comp-E0x.png
 
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ci139

Joined Jul 11, 2016
2,008
muhahaa (im so stupid)
_Draft-AD-comp-E03.png
i only play computer games such as LT Spice -- i usually dont build/test those things -- !! be aware
 

kubeek

Joined Sep 20, 2005
5,796
Hello. I tried a basic circuit with AD8561 comparator. The circuits and the output is under this post. I wonder that if this 800us rising and falling time can be reduce or not. Thanks in advance!/QUOTE]Where do VCC and VEE in your simulation come from? And where did you get the model of that chip?
 

ronsoy2

Joined Sep 25, 2013
71
This could be a measurement problem, not the IC itself. I threw it together and the photo below shows the results. The tremendous overshoot is simply because I used a 6 inch ground lead on the scope clip, it is not really there. But you can see the risetime is well under 10 ns, as the data sheet shows it should be. Are you by chance using a x1 probe? That might load down the output but even that seems like it should give about a hundred nanosecond or so rise. Use a x10 probe and a short as you can get away with ground lead to see the true risetime. testerphoto 001.jpg
 
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