Hi everyone~

I am designing a two-stage op-amp with PMOS as input transistors, with the first stage as a differential pair, while the next stage is a CS amplifier. I have designed the schematics as of below in LTSpice:

I have to design the above according to the specifications:

1) Supply voltage: 3 V (Single supply)
2) Open-loop DC gain: > 75 dB (I will be choosing 100)
3) Gain peaking: < 2 dB (ratio of maximum gain to gain at DC)
4) Unity gain bandwidth: > 20 MHz
5) Phase Margin: > 60 degree
6) CMRR : > 70 dB
7) Output voltage swing: > 1.0 V (Peak-to-Peak)
8) Offset voltage: < 2m V
9) Supply current: < 600 uA
10) Output load capacitance: 0.2 pF
11) Maximum channel width: 1000um

I have performed the following calculations by hand:
Page 1:

Page 2:

However, when I did a transient simulation in LTSpice, I realized that there is clipping at the top and bottom of the waveform, and I am lost at reducing the output voltage swing. The graph is shown below:

I understand that the clipping is because the voltage has swung beyond Vod6 and Vod7 (overdrive voltages for M6 and M7). May I ask how should I reduce the output voltage swing?

Thank you so much!

 

Have you considered reducing the amplitude of the input signal?

 

Have you considered reducing the amplitude of the input signal?

Ah yes, but I am not sure how I should reduce it.

I understand that the input amplitude should be set as: Vswing(p-p) / Av , where Av is the gain.

However, I have not set the gain before I designed the system.

I was wondering if I should calculate the gain from my design above to determine Av before applying: Vswing(p-p) / Av. May I ask if this is the right approach? I will keep in mind also, that I must multiply the gain from the first stage and second stage~

Thank you so much once again.

 

(some text removed for clarity)
I was wondering if I should calculate the gain from my design above to determine Av before applying: Vswing(p-p) / Av. May I ask if this is the right approach?

It sounds like a good exercise. Whether it is the right approach depends upon what your goal is.

 

It sounds like a good exercise. Whether it is the right approach depends upon what your goal is.

Thank you for your advice~ May I ask what do you mean by my goal?

My goal is to prevent clipping in the output waveform.

I have tried to put in 0.15m as my input in “SINE(0 0.15m 1k)" and the waveform swings nicely, as seen below:

However, this also means that my Av is 1.2/(0.3*10^-3) = 4000, but when I tried to calculate using the above method, the greatest Av I got was 1923, and hence I got confused a little.

I made a mistake above, as the formula should be Av = Vout,p-p/Vin,p-p

Thank you!

 

Ah I'm sorry. I think I made mistake just now. My value of Av, should be this large (though it should be even larger) as I have forgotten it is in arbitrary units.

I am trying to increase the gain at the moment. It is currently at around 67dB but I need it to be more than 75dB.. :'(

 

I am trying to increase the gain at the moment.

The gain at what frequency?

Is this homework?

Care to share your .asc file?

 

The gain at what frequency?

Is this homework?

Care to share your .asc file?

Hello! Thank you for your reply~ There is no specific working frequency for this model and yes this is homework. haha~

Yes, sure~ Thank you once again!

 

It appears the the transistors you use are not standard transistors in the LTSpice package, and I'm too lazy to try to copy all the work you've done. You'll have to post another .asc with standard transistors or also post your models. Note that the nmos4 and pmos4 both provide access to the body - although it doesn't look like you're doing anything with the body of the transistors in your design so you could get away with using the nmos and pmos models instead as well.

You keep saying you need more gain. My question of "The gain at what frequency?" was a hint, Danielson.