Hello, I'm designing a PFC based on the next configuration:



The design is for 400W. Using FAN9611 controller.
The problem is that the mosfets get considerably hot and I would like to know if there is a way to reduce the power losses on them.
I'm measuring Vds and the current through the transistor using a current probe.





The yellow curve represents Vds across the mosfet, the blue is the current Is and the red one is the power Vds*Is
Im zooming on the peaks of the red curve. The switching event takes around 104ns. The peak power loss during switching is around 450W.
The RMS current through the transistor is 600mA with around 1.5A peak.

I'm using the transistor FCB070N65S3 whith the following characteristics:

Vdss: 650V
Rds(on): 70mOhm
Id(max): 44A
Qgs: 18nc
Qgd: 30nC
ESR (is that Rg?): 0.6Ohm
Coss: 68pF
Ciss: 3090pF

I'm using a configuration like this one to drive the mosfets:

Can you please explain to me why after the mosfet is turned off there is still current flowing throug it?
Could you please point me in the way to understand which of these factors are important to reduce the losses?

Edit:
Here is the exact circuit I'm using to drive the mosfets, I didn't measure connecting it directly to the IC, but I tried a some time ago and it was noticeable worst.



I also measured Vgs




Thank you!

 

How well does it work without the transistor buffer? The FAN6911 has an output capable of 2A, and that should shift 50nC in 25ns.
The buffer would normally have the resistor between emitters and MOSFET gate as it damps any oscillations on the gate. I wonder what the gate waveform looks like?

 

How well does it work without the transistor buffer? The FAN6911 has an output capable of 2A, and that should shift 50nC in 25ns.
The buffer would normally have the resistor between emitters and MOSFET gate as it damps any oscillations on the gate. I wonder what the gate waveform looks like?

Thank you for your reply, I edited my post with the info