Hello all,
This seems like an excellent place to look for a novel solution to a problem that's not too tricky, just looking for the most reliable outcome to minimize board space.

So, I need to control 32 data lines, more specifically, supply a common voltage source to one OR MORE selected lines at any given time. Using existing components to draw an analogy, it would be most desirable to have something that functions like a 32 demux, but instead of a single output routed from the input it would need to be able to hold 2 or more, up to 32 outputs at the input value. Of course it would need to still have output selection, a 5-bit selection for this still works, but an enable switch would simply hold this state (high) for an addressed output until that same output was selected and instructed to change state (low). A reset would be very handy too, this would in effect tie all outputs low.

Anyone out there know of something that can knock this out in one package? Seems like it shouldn't have much of a noise and/or reliability issue in operation as demuxers are used and pretty solid if you put a little more $ up-front.
Thanks in advance,
b

 

It sounds like a 32-bit addressable latch.
Here is the 8-bit version
http://www.nxp.com/documents/data_sheet/74HC_HCT259.pdf
You can do this in an FPGA, but it might be kind of expensive.
I am quite sure there is no OTS part that will do this.
We used these parts all the time for peripheral device control registers.

 

What you are describing is a SSAD - a Source Select At Destination routing switcher. Maxim has several chips left over from the low res video markets, but most of them are "square" routers like 4x4, where you want 1x32.

Four 259's and one 2-line to 4-line decoder get you 32 addressable outputs. Other than a CPLD, that's as simple as it gets. You will need a small circuit to create a delayed strobe pulse to drive the Latch Enable inputs, but you would need that even if there were a single chip to do all 32 latches.

ak

 

Golden answers people, thank you!
I guess I need to approach this differently, like a "register" of sorts outboard from a microcontroller. Ultimately I'm trying to conserve the GPIO on the uC as given other vitals, it's going fast... So I'm thinking I could do this enable feature using a combination of 32 enabled/disabled lines as a 5-to-32 decoder stage (made from smaller decoders), then a 32-bit SR latch IC to hold a "mask" indicating which lines are selected, just flipping bits as needed. This way, the latch IC should provide a reset line and I'll knock that out on the fly.
Does this sound kosher, am I not thinking about this right...?

 

Except for the 32 bit SR latch. There is a quad SR latch chip in 4000 series CMOS, but now you're up to 8 latch chips instead of four 259's.

ak

 

Ok AK, I'm assuming a 259 is a 3-to-8 decoder nomenclature...? Also, could you elaborate a touch on how these latches provide the bit-position "memory"? My apologies, it's a tad foggy to me, does each 3-to-8 have an array of latches (T or D?) that are clocked (strobed) to achieve this?