![8ohm load design.png 8ohm load design.png](https://forum.allaboutcircuits.com/data/attachments/310/310879-2c50b8b5b13c758b0ef09b82e8da066f.jpg)
Now that I understand Electronics, I tried to implement a simple "bad" sound amplifier to test my knowledge, and I found impossible to drive an 8Ω load without attenuating the signal!!!
The following are not exactly the real calculations, but close enough. I have changed some parameters (RC, and Rx bias), but the idea of the challenges is the same.
First I created the first stage at Q1 with Ic = 1mA and Vc = Vcc/2 = 10V. I immediately noticed that the requirement for Vc = Vcc/2 with a big RC, COMPLETLY resticts the voltage at the base!!! I had to use Vb = 1V, in order to achieve the 1mA current and Vcc=10V!
Challenge 1: Trade-off between base voltage and Vcc, current requirements!!! Because the input is only 5mV, for this case 1V in the base is enough to not cut off the transistor.
For the Rin calculations, I'm assuming that the parallel of the Voltage Dividers resistances is high enough (which it is) to approximately give the Rin without including them
I will also assume the min Hfe value of the transistors I have in my home, which is B=100.
Final results in the first stage:
\( gm_{1} \approx \frac{1mA}{25mV} = 0.04S \) \( \frac{1}{gm_{1}} = 25Ω \)
\( Rin_{1} \approx \frac{B}{gm_{1}} + (B+1)Ree1 \approx \frac{100}{0.04} + 101 \cdot 47 \approx 7.247k\Omega \)
Rin should be good enough, I do not expect high Signal input resistance (smartphone).
\[ Av_{1} = \frac{Rc}{\frac{1}{gm_{1}} + Ree} = \frac{10k}{\frac{1}{0.04} + 47} = 138V/V \]
Stage 3 Power Amp:
Of course, I can not drive the 8Ω load directly because RC//8Ω will give 8Ω and the gain will be reduced a lot!!!
First, I thought to add the power (common collector) amplifier Q3.
Challenges: Increasing the bias current of the power amplifier, results in a small Rin, which counterattacks the requirement of a Rin3 >> Rc = 10k!!!
Also, this time I need a bigger Vb3, because the output of the first stage will be bigger in amplitude!!!!
Increasing Vb3, results in an increased voltage drop in the RE3, which results in a bigger current or bigger RE3!!!
I choose to use a 50mA bias current which results approximately in an Rin3 = 860Ω!!! The good thing is that 1/gm3 gets really small, and the parallel resistance of RE3//RL does not change the unity gain that much of the power emitter follower.
So I thought, let's use that and use a Voltage Buffer in between what gives a big Rin2 >> Rc = 10K and Rout2 << Rin3 = 860Ω??
Stage 2 Voltage Buffer:
Now I can't make this voltage buffer to work...
Decreasing the bias current results in big Rin2, but in a BIG RE2 that destroys the gain in the third stage.
Also, requiring a big Vb2 =6.66V, increases the voltage drop at RE2 which also leads to a bigger RE2 that destroys the gain in the third stage
OR a bigger bias current that lowers Rin2 and destroys the amplification of the first stage...
I don't know what to do...
I decided to put Vb1 = 1v => RE2 = 1KΩ => IC2 = 1mA which gives Rin2 = 103.5KΩ but Rout = 1k > RIN3 = 860Ω that attenuates the third stage...
Conclusion:
It seems that analog design is actually much harder than I anticipated.
What should I do, to fix the above circuit?
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