Hi Guys,

Could someone explain me page 1 of this article?

I assume that the gate-source is a cap and for a cap, V is integral of I so Vgs should keep on increasing linearly with a constant I.

What is happening?

Thanks

 

I think they are referring to how the family of curves looks like a family of constant current
sources. This is a P channel device.



As you can see once Vds gets sufficiently high, for a given Vgs, the Id stays constant
for larger Vds.

As for charging cap, not sure if thats what they are trying to infer, because the
way its connected Vgs = 0. Maybe someone else can see a point in this.
If Vgs is 0 then the Isrc in source lead would be charging reverse transfer C
and Cds. Up to the point there was no V across the current source, eg. out of
its compliance range.

Basically i too am confused......

Regards, Dana.