the most significant address lines (A15,A14,A13) would be used for the MUX while the rest of the address lines are used for the ROM (A0-A12) since 8Kx8 ROM required 13 address lines.

 

the most significant address lines (A15,A14,A13) would be used for the MUX while the rest of the address lines are used for the ROM (A0-A12) since 8Kx8 ROM required 13 address lines.

You could do it that way, but it just seems more natural to use the low bits to pick off the individual bits from the byte. That meshes up with the notion of each address in the ROM serving 8 consecutive addresses in the module. In most applications it would probably provide better performance, too, but that would depend on a lot of things.

 

I believe that ericgibbs made a mistake when he change the data width from 8 bits to 16 bits. You only need to have it 8 bits wide "32Kx8 memory module"

hi LCD,
Thanks for heads up, I did misread the question as 16 Bit wide Data.
E

 

Consider the ROM first. 8Kx8 ROM devices,
You need 2 pairs of 8K by 8 ROM, to give 16 Bit WIDE and 16K Long,, Start Address decode 0000h

For the RAM , a 4 pairs of 8Kx4 RAM devices to give 16 Bit WIDE data and 16K Long, Start address 2000h. [ 0010,0000,0000,0000]

Sorry, can I ask why the ROM starts at 0000H and RAM starts at 2000H? Cause the question says the memory module starts at 2000H? Shouldn't it be both start at 2000H?

 

Sorry, can I ask why the ROM starts at 0000H and RAM starts at 2000H? Cause the question says the memory module starts at 2000H? Shouldn't it be both start at 2000H?

No, it states that the RAM follows the ROM, so ROM starts at 2000H and the RAM starts 16K later to give you 32Kx8 of memory.

 

Okay, thanks a lot

 

Sorry, can I ask why the ROM starts at 0000H and RAM starts at 2000H? Cause the question says the memory module starts at 2000H? Shouldn't it be both start at 2000H?

Think about that for a moment. How could two different memory elements be at the same address?