Question:

Using 8Kx4 RAM devices and 8Kx8 ROM devices, a 32Kx8 memory module needs to be designed for a 16bit memory address system such that the first 16K consists of ROM and the next 16K of RAM. The memory module starts at address 2000H.

(i)Draw a memory map of the memory module using hexadecimal notation. Show clearly the memory ranges occupied by the different memory devices.
(ii)Draw a neatly labelled circuit diagram showing how the memory module can be realized using the memory devices and additional logic gates.

I was not able to get 16 address line since it required 2 nos of 8Kx8 ROM and 4 nos of 8Kx4RAM and each required 13 address lines and using a 3-to-8 decoders, it required another 3 address lines. The memory module starts at address 2000H which required another 4 address line. It would total up to 13+3+4 = 20 address line which exceed the limit of 16 bit.

I really need help on this homework, please help. Thanks a lot.

 

hjh

 

hi IcyIcy,
You should be able to answer this question, IF you understand the first memory Thread you started.
The method is to connect the lower order address lines to ALL the ROM and RAM, then the leftover higher order Address lines into the decoder chip.
Try it and post what you think.

Hint: The ROM and RAM share the same Data and Address lines.

 

hi IcyIcy,
You should be able to answer this question, IF you understand the first memory Thread you started.
The method is to connect the lower order address lines to ALL the ROM and RAM, then the leftover higher order Address lines into the decoder chip.
Try it and post what you think.

Hint: The ROM and RAM share the same Data and Address lines.

But I am not sure if it is meant by A0-A12 connects to RAM and ROM then A13-A15 connect to decoder to trigger each chip (6 chips). I got confused with the address lines where it state that the module starts at 2000H. Does it mean that 4 address line has to be reserved for that (A15-A12) or can I used it for my decoder?

 

But I am not sure if it is meant by A0-A12 connects to RAM and ROM then A13-A15 connect to decoder to trigger each chip (6 chips). I got confused with the address lines where it state that the module starts at 2000H. Does it mean that 4 address line has to be reserved for that (A15-A12) or can I used it for my decoder?

Eh... there should be 2 pair of 8K x 4 RAM and 2 nos of 8K x 8 ROM which means I can use 2-to4 decoder.

 

Using 8Kx4 RAM devices and 8Kx8 ROM devices, a 32Kx8 memory module needs to be designed for a 16bit memory address system such that the first 16K consists of ROM and the next 16K of RAM. The memory module starts at address 2000H.

Consider the ROM first. 8Kx8 ROM devices,
You need 2 pairs of 8K by 8 ROM, to give 16 Bit WIDE and 16K Long,, Start Address decode 0000h

For the RAM , a 4 pairs of 8Kx4 RAM devices to give 16 Bit WIDE data and 16K Long, Start address 2000h. [ 0010,0000,0000,0000]

 

Consider the ROM first. 8Kx8 ROM devices,
You need 2 pairs of 8K by 8 ROM, to give 16 Bit WIDE and 16K Long,, Start Address decode 0000h

For the RAM , a 4 pairs of 8Kx4 RAM devices to give 16 Bit WIDE data and 16K Long, Start address 2000h. [ 0010,0000,0000,0000]

Sorry can I ask why isn't it 2 set of 4 nos. 8Kx4 RAM devices but, 4 pairs of 8Kx4RAM devices?

 

2 set of 4 nos. 8Kx4 RAM devices

Sorry, I'm confused. What does nos mean?

 

Sorry, I'm confused. What does nos mean?

number

 

I believe that ericgibbs made a mistake when he change the data width from 8 bits to 16 bits. You only need to have it 8 bits wide "32Kx8 memory module".
Your memory would look like this
The yellow squares are the 8Kx8 ROM and the green rectangles are the 8Kx4 RAM (8k+8k+8k+8k=32K).

 

Thanks a lot for your help, I have a better understanding now.

 

Sorry, I have another question, is it ok that the 2 pair of RAM and 2 number of ROM shares the same bit (A0-A15)?

When I draw the module map, I realise that it is the same.

Starts from 0000H:
[0000 0000 0000 0000 0000]
[0001 1111 1111 1111 1111]
[0000 0000 0000 0000 0000]
[0001 1111 1111 1111 1111]

Starts from 2000H:
[0010 0000 0000 0000 0000]
[0011 1111 1111 1111 1111]
[0010 0000 0000 0000 0000]
[0011 1111 1111 1111 1111]

 

... is it ok that the 2 pair of RAM and 2 number of ROM shares the same bit (A0-A15)?
When I draw the module map, I realise that it is the same.

Yes, since the RAM and ROM are selected by the 13th and 14th address line.

BTW, you have too many blocks in your table, it should be:
Starts from 0000H:
[0000 0000 0000 0000]

 

Yes, since the RAM and ROM are selected by the 13th and 14th address line.

BTW, you have too many blocks in your table, it should be:
Starts from 0000H:
[0000 0000 0000 0000]

Thanks a lot for clarifying my doubts. Could I ask one more question?

Currently, I have done expanding circuit using the data line that is smaller or equal to the data line that I am going to realise (16Kx4 RAM to realise 64Kx16 RAM). But, how do I realise a 64Kx1 ROM from a 8Kx8 ROM?

 

Thanks a lot for clarifying my doubts. Could I ask one more question?

Currently, I have done expanding circuit using the data line that is smaller or equal to the data line that I am going to realise (16Kx4 RAM to realise 64Kx16 RAM). But, how do I realise a 64Kx1 ROM from a 8Kx8 ROM?

Q1) How many address lines do you need for the 64Kx1 module?
Q2) How many data lines do you need for the 64Kx1 module?
Q3) How many address lines do you have for the 8Kx8 ROM?
Q4) How many data lines do you have for the 8Kx8 ROM?
Q5) For each address of the 8Kx8 ROM, how many different addresses of the 64Kx1 module must it serve?
Q6) How many additional address bits does this represent?
Q7) How can you use those additional address bits to spread the data from the ROM across the addresses in the module they need to serve?

 

... how do I realise a 64Kx1 ROM from a 8Kx8 ROM?

The easiest way I can think of is: when you read data, the ROM sends the data byte to a parallel to serial buffer and then the data is transfered one bit at a time to the microprocessor.
To write to memory, you would need to send 8 bits into a serial to parallel buffer and then write the data byte in the buffer to memory.

 

The easiest way I can think of is: when you read data, the ROM sends the data byte to a parallel to serial buffer and then the data is transfered one bit at a time to the microprocessor.
To write to memory, you would need to send 8 bits into a serial to parallel buffer and then write the data byte in the buffer to memory.

Can i use a 8-to- 1 multiplexer to solve?

 

Can i use a 8-to- 1 multiplexer to solve?

Yes, I forgot about those chips.
But to do a write operation, you would need to read a byte from the ROM, replace the single bit, then write it back to ROM.

 

The easiest way I can think of is: when you read data, the ROM sends the data byte to a parallel to serial buffer and then the data is transfered one bit at a time to the microprocessor.
To write to memory, you would need to send 8 bits into a serial to parallel buffer and then write the data byte in the buffer to memory.

In general this wouldn't be the case because, again in general, the ROM is not necessarily accessed sequentially. But for applications where it is known that it will be read sequentially, this would be a quite reasonable way to go.

 

Can i use a 8-to- 1 multiplexer to solve?

Yes, that is what I had in mind. How many address lines would be used up by the MUX? How does that fit with the list of questions I asked?

Note that I asked those questions for a reason. If you understand WHY each of those questions is relevant and how to answer them, then you are well on your way to easily being able to handle all of the memory module questions you have been struggling with.