while compiling my program written for modular division & montgomery modular multiplication in verilog, i often get the following error...
----Can not simplify operator REM.
----Loop has iterated 64 times. Use 'set -loop_iteration_limit XX' to iterate more.
can u tell me what it is?
----Can not simplify operator REM.
----Loop has iterated 64 times. Use 'set -loop_iteration_limit XX' to iterate more.
can u tell me what it is?