while compiling my program written for modular division & montgomery modular multiplication in verilog, i often get the following error...

----Can not simplify operator REM.
----Loop has iterated 64 times. Use 'set -loop_iteration_limit XX' to iterate more.

can u tell me what it is?

 

This really belongs in the programming forum, but I'll take a stab at it

Perhaps you're trying to use REM to indicate a comment, but REM isn't valid for indicating program remarks
or - you have some sort of piping command on a comment line that's causing the compiler to pick it up anyway, but it doesn't know what to do with the data after the piping command. For example, in MS-DOS .BAT/.CMD files, if you use < or > piping operators after a REM, they are still executed.

 

I'm not familiar with Verilog, but if you provide the code that caused the error, perhaps someone could help.

 

My guess at "Loop has iterated 64 times. Use 'set -loop_iteration_limit XX' to iterate more." is that VLog has a built-in safety to keep it from an infinite loop. Enter the command they suggest using, say, 100 in place of the 'XX', and see if you get the same error. If so, there is probably something wrong with the coding.

--Rich