How to block stray signals from reaching my h-bridge

Thread Starter

rfengineer28

Joined Apr 28, 2021
71
Hello all, currently I am implementing digital design into my H-bridge for added security. However, I have been running into an issue where I am getting stray voltage signals getting to my gate drivers and I would like to find a way to completely eliminate those. I have 4 power MOSFETS hence 4 different signals. I was thinking if maybe a multiplexer would solve my issues but I am unsure of that, it would definitely have to be a mux that takes in 4 inputs but then again i could be wrong. Any input would be appreciated.
View attachment 270289
 

Ian0

Joined Aug 7, 2020
5,556
Gate drivers are good. They are designed to prevent signals from the MOSFETs getting back to the drive circuitry.
 

Ian0

Joined Aug 7, 2020
5,556
What is meant to happen if the PWM signal is at 0%?
I would expect that the output of the bridge should be at zero, in which see the high side MOSFET should be OFF, and the low side. MOSFET should be on, which is the drive signals you have.

Why don’t you use a half-bridge driver IC which takes a PWM input and deals with the dead time itself? Some of them even have adaptive dead-time control which test the output of the bridge to decide when to switch.
 

Thread Starter

rfengineer28

Joined Apr 28, 2021
71
What is meant to happen if the PWM signal is at 0%?
I would expect that the output of the bridge should be at zero, in which see the high side MOSFET should be OFF, and the low side. MOSFET should be on, which is the drive signals you have.

Why don’t you use a half-bridge driver IC which takes a PWM input and deals with the dead time itself? Some of them even have adaptive dead-time control which test the output of the bridge to decide when to switch.
The picture above is showing the output with 0% pwm, I am using gate drivers but they don’t have dead time or interlocking. The ones I have tried that have had dead time built it haven’t worked as they don’t match the time delays of the Mosfets I am using. All I am trying to do is block out v(2) because usually it’ll send the +5 into driver when I am driving in the opposite direction and I don’t like that. Outputs 1 and 2 correspond to 1 direction of the motor. 1 is left side high side fet and 2 is right hand low side fet. I just don’t want that low side signal to arrive in my bridge when it’s not supposed to, but the logic is high when I’m not pulsing because of the inverter.
 
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