hi i have question
i know that a n-channel jfet needs a negative voltage on its gate to operate but i found on many sites a jfet circuit with a voltage divider biasing network just as a npn common emitter circuit
how could it possibly work like this ??
isn't it supposed to be biased like this circuit :
can u please tell me which one is the right one and if they are both right how can the first circuit be able to bias the gate at a negative voltage ??
i know that a n-channel jfet needs a negative voltage on its gate to operate but i found on many sites a jfet circuit with a voltage divider biasing network just as a npn common emitter circuit
how could it possibly work like this ??
isn't it supposed to be biased like this circuit :
can u please tell me which one is the right one and if they are both right how can the first circuit be able to bias the gate at a negative voltage ??