how to bias a jfet right

Thread Starter

Ghina Bayyat

Joined Mar 11, 2018
139
hi i have question
i know that a n-channel jfet needs a negative voltage on its gate to operate but i found on many sites a jfet circuit with a voltage divider biasing network just as a npn common emitter circuit

how could it possibly work like this ??

isn't it supposed to be biased like this circuit :

can u please tell me which one is the right one and if they are both right how can the first circuit be able to bias the gate at a negative voltage ??
 

AlbertHall

Joined Jun 4, 2014
12,347
if they are both right how can the first circuit be able to bias the gate at a negative voltage ??
They are (or could be, depending on values) both right.
The gate needs to be negative of the source so in the second circuit the gate will be at some positive voltage but as long as the source is at a higher positive voltage then the gate will be negative of the source.
 

Thread Starter

Ghina Bayyat

Joined Mar 11, 2018
139
They are (or could be, depending on values) both right.
The gate needs to be negative of the source so in the second circuit the gate will be at some positive voltage but as long as the source is at a higher positive voltage then the gate will be negative of the source.
I get it now so the gate doesn't have to be realy negative but more negative than the source
and if i have a dual rail supply voltage like a battery i should rise up the source voltage by using the resistor Rs right ??
This means that i should choose Rs to be greater than Rg2 ??
 

crutschow

Joined Mar 14, 2008
34,464
Why does everyone say "n-channel"? I understand its a field effect unipolar transistor, but that is not a good excuse for me.

"n-channe" == npn
"p-channel" == pnp.
Because those are not equivalent.
npn and pnp are not descriptions of field-effect transistors, they are descriptions of bipolar junction transistors.
That's why everyone says n-channel (or p-channel) for junction FETs. :rolleyes:
 
Last edited:

ian field

Joined Oct 27, 2012
6,536
hi i have question
i know that a n-channel jfet needs a negative voltage on its gate to operate but i found on many sites a jfet circuit with a voltage divider biasing network just as a npn common emitter circuit

how could it possibly work like this ?? isn't it supposed to be biased like this circuit :

can u please tell me which one is the right one and if they are both right how can the first circuit be able to bias the gate at a negative voltage ??
Its pretty much the same as a thermionic triode with suitably proportioned voltage levels.

The divider bias method sometimes pops up in older "circuit compendiums", I've never seen an explanation for it. Maybe necessary in the top section of a cas-code stage though.
 

OBW0549

Joined Mar 2, 2015
3,566
The divider bias method sometimes pops up in older "circuit compendiums", I've never seen an explanation for it.
Using a voltage divider to bias the JFET's gate a bit above ground allows the source resistor, Rs, to do a better job of stabilizing the circuit's operating point. Without it, drain current is entirely dependent on the JFET's characteristics, and both Idss and Vgs(off) can vary by 3:1 or even more from unit to unit.

Because of the spread in characteristics, JFETs are notoriously tricky to bias in a consistent, repeatable way-- which is a big part of the reason you don't see them used more often.
 
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