how reduce lost bits in the circuit with 16-bit ADC?

Thread Starter

siavosh1

Joined Apr 16, 2019
8
Hi
i'm designing the circuit that want to achieve 16bit resolution or 65536 steps.
ADC input voltage rang = 4.096v
adc chip : max1169
1 step = 62.5 uV
i use 5k potentiometer between vcc and analog ground for create simple input signal to ADC and see the input changes in PC .
you can see circuit summary in here
1.png .
i use the opamp buffer for Vin according to MAX1169 evaluation kit circuit and drive this ADC like the datasheet. but instead of (opamp) MAX4430 i use AD8055a that give me high slew rate value. and send the data value to the ARM at91sam7s64 . PC software receive data with COM port.
at the first time i had 200mv (3200 steps) ripple in output. but by using some tips, destructive effects of ripple and noise reduced to 2.75mv ( 44 steps).
at now i can reduce this value around to 1/3 or 0.9mv (14 steps) and next step to achieve to 1 step. but i have two problem.
problem 1 : when i use the battery i don't have a good dc output line (unstable) that you can see in the pictures :
battery is lipo 2cell 7.4v .
total circuit current = 50mA
bat1.jpg
bat2.jpg

but when i use power supply the output dc line (red line) have a good seems :
psup1.jpg
psup2.jpg
problem 2 : how to achieve from 14 step to 1 step (16bit resolution) ?
 
Last edited:

sagor

Joined Mar 10, 2019
108
Data sheet states that the Relative Accuracy is +/- 2 LSB (least significant bits). That means you may never be sure of any 1 step "accuracy", as +/- 2 LSB error could be 2 steps above or below the true value when calculated by the chip. While it is a 16 bit A/D, that does not mean it is 16 bit accuracy, all A/D converters have a small degree or error in conversion. All 16 bit means is that it returns a 16 bit value that includes conversion errors.
 

danadak

Joined Mar 10, 2018
3,573
1) Using your DSO on in finite persistence look at supply rail of A/D, what is
its pk-pk noise ? The datasheet has no PSRR specs on A/D, Vref.....which is
unfortunate.

2) Not all bypass caps have equal ESR for same capacitance, look at data sheets
carefully.


The OpAmp will pick up noise via coupling and its own PSRR on its supply rail
from other devices on rail.

3) Bypass ADC with both ploymers and ceramics, MLC, to get the noise down.

4) Layout and ground bounce are crucial -

https://www.cypress.com/documentation/application-notes/an57821-psoc-3-psoc-4-and-psoc-5lp-mixed-signal-circuit-board-layout


Regards, Dana.
 

dendad

Joined Feb 20, 2016
2,983
Layout of your circuit will be important, as will power supply stability and voltage reference.
Quality of the resistors and other components too.
when i use the battery i don't have a good dc output line (unstable)
You need to fix the power supply. That is the foundation of it all.
But as stated above, you will not get single bit accuracy results. If you need 16 bits, try an 18bit ADC. The more bit you are after, the more important the quality of design and construction becomes.
 

Thread Starter

siavosh1

Joined Apr 16, 2019
8
thank for all replies .
Using your DSO on in finite persistence look at supply rail of A/D, what is
its pk-pknoise ? The datasheet has no PSRR specs on A/D, Vref.....which is
unfortunate.
max1169 datasheet : "Note 7: ADC performance is limited by the converter’s noise floor, typically 225μVP-P."
225uV = 3 step
max1169 datasheet : "Power-Supply Rejection Ratio PSRR VAVDD = 5V ±5%,min =5 and max 16 LSB/V"
according to this information i get the answer of second problem. I think in the best situation might be able to reduce 14 steps to 8 or 7 but not 1 or 2.
3) Bypass ADC with both ploymers and ceramics, MLC, to get the noise down.
i use tantalum and ceramic in circuit and i use this tips.
4) Layout and ground bounce are crucial -
i use star grounding and short wire . but at now this is a test board and aren't PCB . i think in PCB i get better result.

but i don`t give the answer for problem 1. i want reduce 44 step to 14 steps. if figure out whats happens when i use battery and the reason of unstable behavior in dc line. how can i control this behavior ?
battery model : (2 X NCR18650BE 3.7v 3200mAh Panasonic)
bat1-detail.jpg
 

crutschow

Joined Mar 14, 2008
23,297
You can always average the digital output to reduce the noise, at the expense of a slower response time.
 

Thread Starter

siavosh1

Joined Apr 16, 2019
8
You can always average the digital output to reduce the noise, at the expense of a slower response time.
i use average loop in Micro-controller for every 10 samples but i can't get more than this because some data will be lost
 

Thread Starter

siavosh1

Joined Apr 16, 2019
8
These pdfs are excellent !! thank you a lot
at now , i have 44 steps error that mean ENOB around the 10bit ( SNR=61.96dB ) that really not good ( in datasheet SNR = 87~90dB).
if i want to go 16bit :
16-12= 6 bits
fos = 4^6 fs ===> that mean i need 4096 time faster . fs= 19 Ksps , fos= 4096*19ksps = 77.824 Msps . MAX1169 can`t support this sample rate . but i do virtually with software and you can see it here :
bat2-detail.jpg
original ADC output signal : white color
after averaging : red color
the part of signal that can modeled with white noise : between yellow color lines
the part that show reduced noise effect : between green color lines
but my problem is blue area. that we can`t model it by white noise!
i think the problem is in power supply circuit (poor circuit) and if we have the better solution for it this problem will be solved.
maybe if i replace the battery this problem solve but i need a solution for this in circuit design because this behavior maybe happens for another battery in next week or next month and i need to have control it. i just use 7805 regulator for +5 and 7660 for -5 and Ams1117 for +3.3 . the better battery type or regulator or ... maybe useful
What is your suggestion for this part ?
 
Top