How is the S-element mapped in a SPICE .subckt?

Thread Starter

virtegmrg

Joined Sep 11, 2023
2
Hi everyone,

I'm working with Cadence Sigrity for PDN analysis, and I'm trying to understand the underlying SPICE syntax it auto-generates when importing a series-extracted capacitor .s2p file.

When I import my series model, Sigrity automatically generates the following subcircuit:

Code:
*Series extracted s-parameter
.SUBCKT capacitor 1 2
S1 1 2 3 2
+ Model =capacitor_series.s2p
V 3 2 0
.ENDS
This node mapping is completely messing with my understanding of how a series component should be wired. Here is my thought process:

  • If the standard mapping for an N-port S-element in SPICE is (P1+ P1- P2+ P2-), then S1 1 2 3 2 implies:
    • Port 1 is between nodes 1 and 2.
    • Port 2 is between nodes 3 and 2.
  • This means P1- and P2- share the same reference node (2).
  • Then, the tool adds V 3 2 0, which is a 0V DC source. This effectively shorts node 3 to node 2.
  • Consequently, it looks like P1-, P2+, and P2- are all short-circuited together!
So, if all of this is short-circuited, wouldn't I just be reading the exact same thing at node 1 as at node 2? How can this block possibly allow current to flow from node 1 to node 2 like a real series component?

Am I misinterpreting how the S1 element maps its ports in this specific SPICE dialect? Does 1 2 3 2 mean something different here?

If my mapping assumption is correct, how does shorting Port 2 (V 3 2 0) and sharing the reference node accurately represent a 2-port series measurement mathematically to the solver?

Any insights into how the solver treats this syntax to extract the actual impedance would be highly appreciated!
 

eetech00

Joined Jun 8, 2013
4,704
Hi everyone,

I'm working with Cadence Sigrity for PDN analysis, and I'm trying to understand the underlying SPICE syntax it auto-generates when importing a series-extracted capacitor .s2p file.

When I import my series model, Sigrity automatically generates the following subcircuit:

Code:
*Series extracted s-parameter
.SUBCKT capacitor 1 2
S1 1 2 3 2
+ Model =capacitor_series.s2p
V 3 2 0
.ENDS
This node mapping is completely messing with my understanding of how a series component should be wired. Here is my thought process:

  • If the standard mapping for an N-port S-element in SPICE is (P1+ P1- P2+ P2-), then S1 1 2 3 2 implies:
    • Port 1 is between nodes 1 and 2.
    • Port 2 is between nodes 3 and 2.
  • This means P1- and P2- share the same reference node (2).
  • Then, the tool adds V 3 2 0, which is a 0V DC source. This effectively shorts node 3 to node 2.
  • Consequently, it looks like P1-, P2+, and P2- are all short-circuited together!
So, if all of this is short-circuited, wouldn't I just be reading the exact same thing at node 1 as at node 2? How can this block possibly allow current to flow from node 1 to node 2 like a real series component?

Am I misinterpreting how the S1 element maps its ports in this specific SPICE dialect? Does 1 2 3 2 mean something different here?

If my mapping assumption is correct, how does shorting Port 2 (V 3 2 0) and sharing the reference node accurately represent a 2-port series measurement mathematically to the solver?

Any insights into how the solver treats this syntax to extract the actual impedance would be highly appreciated!
In spice terms, the circuit is wired as follows:

* The subcircuit defines a component that is named "capacitor" and has two pins "1" and "2"
.SUBCKT capacitor 1 2
* S1 is a VC switch where nodes 1 2 are switch contact nodes, nodes 3 2 are control nodes
S1 1 2 3 2
* S1 definition is continued here, but this statement may be malformed
+ Model =capacitor_series.s2p
* V is a zero valued voltage source that is usually defines a "current meter". It has two nodes 3 2 with a value of zero.
V 3 2 0
.ENDS

Graphically, The circuit looks like this:

1772807976792.png

The spice circuit does nothing.

The file " capacitor_series.s2p" might shed some light on what this is intended to do.
 

Thread Starter

virtegmrg

Joined Sep 11, 2023
2
In spice terms, the circuit is wired as follows:

* The subcircuit defines a component that is named "capacitor" and has two pins "1" and "2"
.SUBCKT capacitor 1 2
* S1 is a VC switch where nodes 1 2 are switch contact nodes, nodes 3 2 are control nodes
S1 1 2 3 2
* S1 definition is continued here, but this statement may be malformed
+ Model =capacitor_series.s2p
* V is a zero valued voltage source that is usually defines a "current meter". It has two nodes 3 2 with a value of zero.
V 3 2 0
.ENDS

Graphically, The circuit looks like this:

View attachment 364292

The spice circuit does nothing.

The file " capacitor_series.s2p" might shed some light on what this is intended to do.
Thank you for your reply,
my intention was to instantiate an S-parameter multiport (n-port) component using the capacitor_series.s2p file, not a switch. I'm using Sigrity for checking some power rails impedance
 
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