My question is particularly regarding the CPU internal architecture. There are multiple clocks in the computer system and the cpu itself is running on the faster clock and rest of the peripherals are working on the slower clock.
Main question is how the CPU manages to control the flow of information (Data or code) between the peripherals for example the CPU sends the signal to the different clock domain such as the slow domain and the data is still in the way to reach to that domain or peripherals and CPU executes instruction fetch cycle of reading the instruction. But the other cycle has still not been completed and when the control unit executes the cycle to read memory address register it will not find any instruction because the data flow is still in progress. how this mechanism is handled ?

 

There are a number of ways to manage it and in any given system involving different clock domains it might be handled differently and a system of any significant complexity probably uses different ways to manage it at different points.

 

One example is serial data transmission. Have a look at..
https://learn.sparkfun.com/tutorials/serial-communication
The UART has it's own clock generator, and after the CPU loads the data in, it has nothing else to do with the transmission. The UART handles it all.
There are others serial controller types too, but this is a start.

Other blocks can be similar. The CPU checks to see if the device is ready to receive data, and if it is, writes it to a register and goes away until next time.

 

In one word: buffers. Usually in the way that the fater system writes a bunch of data in them at its own high speed, and the slower system then reads them at its own slow speed.

 

In the case of say a UART the UART buffer signals an arrival of a byte or word and that issues a interrupt which can be serviced much faster than the UART is operating.
In the case of transmit, the UART has a flag that indicates when the TX register is empty.
Max.

 

it generally doesn't matter. Most peripherals respond as memory locations ans generally implement ready, done bits and interrupts.

Semaphores or disabling interrupts are a method of keeping independent software routines behaving.

Semaphores are odd iittle software tricks taking advantage that increment is one clock cycle.
If a routne wants a resource it can:
test for availability; Does Sepaphore = 0
Increment if available; Semaphore++
Then check it again to see if it's one value higher.; Semaphore =1
If not semaphore = semaphore-1 and it's not yours.

Then check is yet again, to make sure it's exactly 1. If it is, it's your resource.

This banks on increment and decrement not being able to be interrupted.

If two routines try to use the same resource, one gets a 2.

So, with interrupts, it's possible for Semaphore to be 2 or more.