hi,

i'm currently making some TTL logic gates (and DTL and DDL), but i'm noticing that there is some significant voltage drop after each gate, i managed to get 3 logic gates in a row, but with any more gates, it won't work properly.
could anyone please show or explain a circuit that could get this lower voltage(about 2.5V) back to 5V?

 

Schematic ?

 

It goes with the territory. TTL is not CMOS, you work with it's limitations.

 

What do you mean "making them"?

 

2.5 V is a valid TTL logic high level. Why do you want to get it "back" to 5 V?

ak

 

Add a resistor between the output and the power supply. For example 1 kOhm. With a weak load, you get a unit equal to 5 volts.

 

i'm currently making some TTL logic gates (and DTL and DDL), but i'm noticing that there is some significant voltage drop after each gate, i managed to get 3 logic gates in a row, but with any more gates, it won't work properly.

Shouldn't happen with TTL. Post a schematic of what worked and didn't work so we can see what you're talking about.

 

hi,

i'm currently making some TTL logic gates (and DTL and DDL), but i'm noticing that there is some significant voltage drop after each gate, i managed to get 3 logic gates in a row, but with any more gates, it won't work properly.
could anyone please show or explain a circuit that could get this lower voltage(about 2.5V) back to 5V?

The output of a TTL gate is typically in the 3 V to 3.5 V range, even if unloaded. That's the nature of the beast.

But cascading gates should not result in it dropping any further -- you should be able to put an unlimited number of gates in series and the last gate should still produce the same output as the first (with the same load, of course).

So show the schematic of the gate as you are implementing it, because it sounds like it is not truly a TTL circuit.