How can I design an lm555 timer 50% duty cycle for 10 Khz?

Discussion in 'General Electronics Chat' started by asd asd 1, Mar 27, 2017.

  1. asd asd 1

    Thread Starter New Member

    Mar 27, 2017
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    Hi I'm trying to design astable circuit with %50 duty cycle for 10 Khz ( tlow=50us and thigh=50us) by using lm555 timer. There are lots of configurations for %50 duty cycle timer circuits but none of them is not working properly for me. Can anybody help me?
    Thanks a lot.
     
  2. EM Fields

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    Jun 8, 2016
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    If you need precisely 50%, run the astable at 20kHz and feed its output into a divide-by-two circuit, like this:
    555 50% duty cycle.png
     
    Last edited: Mar 27, 2017
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  3. dl324

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    Welcome to AAC!

    The easiest way is to double the timer frequency and use a flip flop.
     
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  4. AlbertHall

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  5. Alec_t

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    The post #4 circuit should give a ~50% duty cycle if the 555 is a CMOS type but, for the more common bipolar type, the fact that pin 3 can only get within a volt or so of the +ve rail makes the duty cycle significantly different from 50%. The deviation is supply-voltage dependant.
     
  6. ian field

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    There is a small duty cycle error because the timing capacitor charges through 2 resistors but only discharges through 1 of them - the discharge transistor must have a current limiting resistor so it doesn't short out the supply during the discharge period, The easiest way to get 50/50 is to drive the CR chain with the output and just ignore the discharge pin.

    You can also have separate charge and discharge resistors and a steering diode in series with each - say for example; you attach a preset pot wiper to the top of the timing cap, you can connect the charge and discharge chains to each end of the pot and trim the mark space ratio to exactly what you want.
     
  7. crutschow

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    Depends upon how precisely you need it to be 50%.
     
  8. ian field

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    Doubling the frequency and dividing by 2 is hard to beat for symetry, but 20kHz is somewhere near where a bipolar starts to get flaky from the frequency drift point of view.

    Using the output to drive the CR network is pretty good - its mainly any difference in the output rise and fall times that could skew the symmetry very slightly.
     
  9. asd asd 1

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    Mar 27, 2017
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    What about the control voltage? Why is it left as not connected?
     
  10. absf

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    Dec 29, 2010
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    Just connect a 10nF capacitor from pin 5 to GND.

    Allen
     
  11. absf

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    Dec 29, 2010
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    555 20K astable.PNG
    Get the R and C from 555 calculator
    555 with counter.PNG
    Output Freq from 555 is about right

    555 with scope.PNG Yellow trace if the o/p of 555 and blue trace is the o/p of 74HC74

    Allen
     
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  12. EM Fields

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    Jun 8, 2016
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    Unless you're in a really noisy environment and jitter on the output is a problem, letting it float is OK.
    If you want / need to decouple it, though, 10nF or so between pin 5 and GND will work.
     
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  13. GopherT

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    @asd asd 1
    The smallest recommended resistor from positive supply to pin7 is 1k.
    With that, a standard astable 555 can be built with a 50.3% duty cycle. So, with rounding errors, it depends on your definition of "50%".

    Resistor from pin7 to pin6 = 67k ohm
    Cap from pin6 to ground = 1 nF

    Replace the 67k with a 47k in series with a 50k multi-turn trimmer to dial in 10k HZ exactly.
     
  14. hp1729

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    Nov 23, 2015
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    Is that output voltage relevant since the threshold and trigger levels are set at 2/3 and 1/3 of VCC?
     
  15. Alec_t

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    Yes, it is relevant when pin 3 provides the current path for both charging and discharging the timing capacitor (unlike in the usual textbook circuit where the positive rail is the charging source and pin 7 is the discharge sink).
     
  16. crutschow

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    Here's a 555 circuit that can be adjusted to 50% duty-cycle:

    [​IMG]
     
  17. ian field

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    That's what most application notes recommend - a lot of people just don't bother.
     
  18. EM Fields

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    And with good reason, since the jitter caused by letting the pin float is almost always negligible and the addition of a decoupling cap would be wasteful and might change the timing formula.
     
    Last edited: Mar 28, 2017
  19. asd asd 1

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    Mar 27, 2017
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    Thank you so much:)
     
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  20. dl324

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    This is from the Signetics Analog Applications manual for NE/SE555:
    upload_2017-3-29_9-22-53.png
    The Nat Semi datasheet implies that 100kHz is typical:
    upload_2017-3-29_9-23-43.png
     
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