Did you ask if it was supposed to be a ripple counter (vs. synchronous)?

Nope

In any case, you should get into the habit of posting schematics (preferrably of the well drawn variety) whenever you're discussing circuits.

Yeah you're right. I'll try my best to clean mine up before turning it in

 

Personally, I think you should go back to the design that was counting erradically, figure out what was wrong, and then connect the two counters.

I can't believe i'm saying this but I figured it out and now it counts from 0-59!!! All that was missing was a 3-input AND gate

 

I can't believe i'm saying this but I figured it out and now it counts from 0-59!!! All that was missing was a 3-input AND gate

Now let's see what you learned.

1. How did you arrive at this solution?
2. Why is the 3 input AND gate delaying reset until after the count of 59?
3. What are the potential problems this solution has?
4. Why are you using different clocks for the two counters? What could happen if they weren't synchronized?

 

Now let's see what you learned.

1. How did you arrive at this solution?
2. Why is the 3 input AND gate delaying reset until after the count of 59?
3. What are the potential problems this solution has?
4. Why are you using different clocks for the two counters? What could happen if they weren't synchronized?

1. I paused and thought about it for a second: I want the first counter to reset not only when reaching 5, but when reaching 5 and having the 0-9 counter also reset. The 2nd and 3rd output pins form the top are 'true' when displaying 5, and the R pin on the 0-9 counter is true when resetting, so I combined these pins' values using an AND gate which is guaranteed to be true only after displaying 59.


2. Because it's only at 59 when all the AND gate's inputs are true

3. I don't know

4. I'm using 2 clocks because I was told to do so. If the two counters were not synchronized, then the left counter will loop through 0-5 and the second will loop through 0-9 continuously, independently.

 

3. I don't know

The circuit has a glitch problem.

To see this

• remove one of the clock generators and connect the remaining one to the clock inputs of both counters
• double click on the clock generator and change the half period parameter to 1 (it defaults to 5)
• run the simulation with a clock period slow enough for you to follow the count
• look closely at what happens when the counter gets to 50

I don't know what the intended purpose of the clock generator period parameter is. I'm trying to find someone at Cedarville University who might know.

 

The circuit has a glitch problem.

To see this

• remove one of the clock generators and connect the remaining one to the clock inputs of both counters
• double click on the clock generator and change the half period parameter to 1 (it defaults to 5)
• run the simulation with a clock period slow enough for you to follow the count
• look closely at what happens when the counter gets to 50

I'll try it. The purpose of this project is to familiarize us beginner students on how to implement counters using registers, so I don't think I'm going to get deducted (my instructor only cares about making it work the way it is - none of the advanced stuff)

I don't know what the intended purpose of the clock generator period parameter is. I'm trying to find someone at Cedarville University who might know.

You're so kind sir thank you!