Hi,

In the photo below showing a a 4 bit counter output and in the attached file is the 4 bit counter. The LTSPICE simulation works as expected as shown in the simulation.

What I need however is when Q3 or possibly Q4 output goes high, a latched output goes high and stays high until reset. Currently, it rolls over on the next clock cycle.

How can I modify the 4 bit counter circuit to stop in the state of the terminal count?

Thanks,

Neko

 

How can I modify the 4 bit counter circuit to stop in the state of the terminal count?

So:

 

So:
View attachment 221921

Hi Danko,

Thanks for your response and post. Yup, that's exactly what I needed.

-Neko

 

So:
View attachment 221921

Hi Danko,

I just noticed something odd. In your sim pic, the count ends on the fifth clock cycle:



When I run your attached sim file, the terminal count ends on the fourth clock cycle:



What am I missing here?

Thanks,

Neko

 

What I need however is when Q3 or possibly Q4 output goes high, a latched output goes high and stays high until reset. Currently, it rolls over on the next clock cycle.

That is what his circuit does - when the third output goes high, the circuit freezes until reset. As the dotted line indicates, you can move the sense line to the 4th output and the circuit will freeze on count 9.

ak

 

Hi Neko,

I just noticed something odd. In your sim pic, the count ends on the fifth clock cycle:

Yes, it is.
Remove "startup" from .tran directive in downloaded file.
It should be stop on the front of fourth high clock pulse.

 

That is what his circuit does - when the third output goes high, the circuit freezes until reset. As the dotted line indicates, you can move the sense line to the 4th output and the circuit will freeze on count 9.

ak

Hi ak,

Sure, I see that. Both Danko and I used the 3rd clock output. Using the circuit that he posted, his circuit for the Q3 output freezes on the fifth leading clock edge. When I run his sim, the Q3 output freezes on the fourth leading clock edge.

I can't reconcile the difference since it the same circuit. Can you explain the difference?

Thanks,

Neko

 

I think the vertical line at 0ms is not a true rising edge. The simulation starts with the clock high.

 

I think the vertical line at 0ms is not a true rising edge. The simulation starts with the clock high.

Hi Chris,

So two things, the pulse profile has no delay meaning the that the first clock rising edge happens at t=0:



As I suggested earlier, I am running the file that was posted that shows the frozen terminal count on the 4th positive clock:



So, what's up?

Neko

 

Hi Neko,

Yes, it is.
Remove "startup" from .tran directive in downloaded file.
It should be stop on the front of fourth high clock pulse.

Removing startup didn't change anything; terminal count still goes high and stays high after 4 positive clock pulses. -Neko

 

Hi Chris,

So two things, the pulse profile has no delay meaning the that the first clock rising edge happens at t=0:

View attachment 222046

As I suggested earlier, I am running the file that was posted that shows the frozen terminal count on the 4th positive clock:

View attachment 222047

So, what's up?

Neko

If I delay the clock by half a period, i.e., 16.66ms, the output goes terminal and locks after 4 positive clock cycles.:



Comments?

Neko

 

Hi Neko,

Yes, it is.
Remove "startup" from .tran directive in downloaded file.
It should be stop on the front of fourth high clock pulse.

Hi Danko,

My sim results show that terminal output stops on the front of fourth high clock pulse regardless of whether startup is in the .tran directive or not. I'm confused?? Why it happened on the fifth cycle in your sim but not mine?

Comments?

-Neko