HM6116A120 RAM Design writable addressable circuit

MrChips

Joined Oct 2, 2009
34,817
You cannot assume that when nothing is connected to the input of a gate that the logic input is 0.
Nothing is not 0.
This is a common mistake made by the uninitiated.

You must have a way to pull the input to logic LOW or logic HIGH.
When interfacing to non-CMOS logic such as 7400, 74LS00 series gates it is preferable to have the switch create a short to GND.
Use a 1k to 5kΩ pull-up to Vcc (+5V).

You must connect /1G and /2G of 74LS244 to the inverted signal of /OE of the SRAM otherwise the two circuits will be in contention.
What does this mean?
The 74LS244 and HM6116 devices both have output capability. You cannot have both in the output state at the same time. Only one device can be enabled as output.

74LS244 is a dual 4-bit bus driver. You do not need two chips unless you find it easier to layout the connections by using two chips.
 

Thread Starter

Steven Diveley

Joined Dec 1, 2018
14
Thank You everyone one the help and advice that was given these past couple days. After extended research on 555 Monostable, and Tri-State buffers, i did end up getting the circuit to work as intended. I really appreciate the extra knowledge I've gained through this thread.
 

MrChips

Joined Oct 2, 2009
34,817
Thank You everyone one the help and advice that was given these past couple days. After extended research on 555 Monostable, and Tri-State buffers, i did end up getting the circuit to work as intended. I really appreciate the extra knowledge I've gained through this thread.
AAC is all about helping one another and learning from each other's experiences.
Please take the time to show us your working circuit and what you had to do in order to get it working.
 
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