Hi guys,
I'm new in here and hope I could get some advices.
I am designing a 100V-28V DC-DC Buck converter but has encountered a problem when choosing a suitable high-frequency switch. As suggested by many designers online, pMOS is preferred for Buck operation. However one big issue is the limitation of the Vgs (typ: +-20V) which I believe is the reason why I could not utilize this as what other designers usually do.
As seen in the attached schematic, in order to turn off the pMOS switch, Vg must not be lower than both Vs and Vd by the threshold voltage indicated by the manufacturer. That is, |Vgs|< |Vth| & |Vgd| < |Vth|. Since Vs is always 100V (because source is tied to +ve terminal of battery) and Vd = 28V (assuming the capacitor is large enough to hold the charge, hence o/p voltage well) and assuming the Vth is -4V, is it correct that to turn switch off, Vg must be > Vs-|Vth| and also Vg > Vd-|Vth| since a pure MOSFET drain and source is interchangeable.
If this is true, a typical pMOS with only Vgs max of 20V could not handle since we must ramp up Vg all the way to 96V and above (for my case) but that also implies the potential difference between Vg and Vd is 68V which is > 20V and thus the FET will breakdown.
And if everything I've explained is true, is there a way to overcome this? TIA.
I'm new in here and hope I could get some advices.
I am designing a 100V-28V DC-DC Buck converter but has encountered a problem when choosing a suitable high-frequency switch. As suggested by many designers online, pMOS is preferred for Buck operation. However one big issue is the limitation of the Vgs (typ: +-20V) which I believe is the reason why I could not utilize this as what other designers usually do.
As seen in the attached schematic, in order to turn off the pMOS switch, Vg must not be lower than both Vs and Vd by the threshold voltage indicated by the manufacturer. That is, |Vgs|< |Vth| & |Vgd| < |Vth|. Since Vs is always 100V (because source is tied to +ve terminal of battery) and Vd = 28V (assuming the capacitor is large enough to hold the charge, hence o/p voltage well) and assuming the Vth is -4V, is it correct that to turn switch off, Vg must be > Vs-|Vth| and also Vg > Vd-|Vth| since a pure MOSFET drain and source is interchangeable.
If this is true, a typical pMOS with only Vgs max of 20V could not handle since we must ramp up Vg all the way to 96V and above (for my case) but that also implies the potential difference between Vg and Vd is 68V which is > 20V and thus the FET will breakdown.
And if everything I've explained is true, is there a way to overcome this? TIA.
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