# Help with making Full Adder using 2 4-to-1 muxes

#### WBahn

Joined Mar 31, 2012
26,398
You are going to have a hard time figuring out how to generate the 2's complement of A using a FA unless you understand how the 2's complement representation for -A relates, mathematically, to the representation for +A. Do you know that?

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#### WBahn

Joined Mar 31, 2012
26,398
I would look at each bit position and add them up and carry over if it is necessary. If I did this right the answer should be: 8.
Yes. But this is what your 8-bit FA will do, assuming you have strung them together correctly. How did you connect the eight separate 1-bit FAs to make the 8-bit FA?

#### mikez

Joined Jan 21, 2013
47
First, draw a schematic in which you have the following signals: A (the 8-bit input), N (the signal that is HI if you want to negate the input, so it comes from your pushbutton) and Y (the 8-bit output). You have available an 8-bit adder and other 2-input logic gates (what are your constraints at this level?). Hint, you can do it with your FA and eight XOR gates.

Note that, because your top level circuit has no B input, you can actually implement the whole thing with just a slightly modified FA circuit (of course, it would no longer be an FA circuit, but that's fine). I wonder if that would be worth some extra credit for you.
For the remainder of the "Sign Changer" symbol I am creating I am not limited to any specific gates or logic. I was only limited on what I could use to create the Full Adder - I am also limited on what I can use for a segment display but that is in the next step of the assignment.

#### mikez

Joined Jan 21, 2013
47
Yes. But this is what your 8-bit FA will do, assuming you have strung them together correctly. How did you connect the eight separate 1-bit FAs to make the 8-bit FA?

I would under the impression that I would assemble the Full Adders into a RCA and that is how I would be taking in the input.

#### WBahn

Joined Mar 31, 2012
26,398
I would under the impression that I would assemble the Full Adders into a RCA and that is how I would be taking in the input.
That's the easiest way to do it and if you are confident that you've done it correctly, then that is great. Just be aware that we haven't had the opportunity to verify your implementation and so if you DIDN'T do it right, things could get confusing down the road. But an RCA is simple enough that you almost certainly did do it correctly.

#### mikez

Joined Jan 21, 2013
47
That's the easiest way to do it and if you are confident that you've done it correctly, then that is great. Just be aware that we haven't had the opportunity to verify your implementation and so if you DIDN'T do it right, things could get confusing down the road. But an RCA is simple enough that you almost certainly did do it correctly.
Here is how I am planning on setting it up - again my amazing MS Paint skills there.

http://i.imgur.com/JUothd0.png

I took a look at what you said earlier with using 8 XOR gates, but am confused on how that will be a solution to my problem. If I tie in Switch0 to both A[0] and B[0] that will not give me the output I desire.

#### mikez

Joined Jan 21, 2013
47
I figured out the answer to my question. I was trying to think of a way that I would have to connect up 8 unique switches to 16 different inputs, but I was thinking about it incorrectly. Since I will be using this to change the sign of my number this will only be needed in the case that my number needs to be changed to a 2's complement. So I will take inputs A[0-7] and connect them up as those will be my switches, but then B[0] = 1 since that will be 0000 0001 which will be needed to be added to my negated values coming from A[0-7].

#### WBahn

Joined Mar 31, 2012
26,398
Here is how I am planning on setting it up - again my amazing MS Paint skills there.

http://i.imgur.com/JUothd0.png

I took a look at what you said earlier with using 8 XOR gates, but am confused on how that will be a solution to my problem. If I tie in Switch0 to both A[0] and B[0] that will not give me the output I desire.

Your 8 switches only control the A inputs (or the B, but not both).

#### WBahn

Joined Mar 31, 2012
26,398
I figured out the answer to my question. I was trying to think of a way that I would have to connect up 8 unique switches to 16 different inputs, but I was thinking about it incorrectly.
Yep.

Since I will be using this to change the sign of my number this will only be needed in the case that my number needs to be changed to a 2's complement.
When you say "this will only be needed...", what is "this" referring to? Connecting 8 unique switches to 16 different inputs? I don't see what else the pronoun "this" can be referring to.

So I will take inputs A[0-7] and connect them up as those will be my switches, but then B[0] = 1 since that will be 0000 0001 which will be needed to be added to my negated values coming from A[0-7].
But you don't want B[0] = 1 when you aren't pushing the button. How will you accomplish that (it's easy)?. Also, what do you mean by "negated values froming from A[0-7]." The A[0-7] are INPUTS to your FA, where are these negated values coming from.

A diagram (and you Paint diagrams are just fine) would be quite helpful.

I think you are either there or very, very close.

Personally, I would tie ALL of the B inputs LO. If you do this, can you see how you would get the 1 that needs to be added into your adder?

#### WBahn

Joined Mar 31, 2012
26,398
Also, you are, probably, going to need to debounce your button inputs...
I don't see why. It is a purely combinatorial circuit. So what if it glitches? It is going to be glitchy anyway.

#### mikez

Joined Jan 21, 2013
47

Your 8 switches only control the A inputs (or the B, but not both).
I should have added a caveat that I only drew 4 out of the 8 on there out of time constraints. I have figured out what I need to do with my inputs and how to handle that. Now my next obstacle is telling it which path to take when I press the button that will change the sign and initiate the 2's complement conversion.

Here is my diagram for that:

http://i.imgur.com/xvSMoQQ.png

Would I want to try and use the enables I have to turn on the muxes within the adders when the button is pressed? For example: input is 0000 0010, where BTN0 = 0 (BTN0 is the control for whether will the number will be positive = 0, or the number will be negative = 1) so then it would bypass the adder since it does not need to be converted to 2's complement, but when the button is pressed this will send a 1 to the enables thus pushing the values through the 8-bit Full Adder and outputting the 2's complement of the input number to the segment displays.

Trying to think of a way to implement this in logic. I guess what I could do is have it go down both paths and then right before it get sent out to the final output I can just use a 2x1 mux and use the BTN0 as the signal selector. Any thoughts on that?

#### mikez

Joined Jan 21, 2013
47
Yep.
But you don't want B[0] = 1 when you aren't pushing the button. How will you accomplish that (it's easy)?. Also, what do you mean by "negated values froming from A[0-7]." The A[0-7] are INPUTS to your FA, where are these negated values coming from.
My B[0] would be hard-coded to be 1. Then B[1-7] would be all connected to GND. Then, for all of my inputs, B[0-7] would be = 0000 0001. Now if I add that to inverted inputs from A[0-7] (1's complement of my input) it would give me the 2's complement. For example:

A[0-7] = 0000 1010
= 1111 0101 (inverted - 1s complement)

B[0-7] = 0000 0001

Sum[0-7] = 1111 0110 (should be the 2's complement)

And Sum[0-7] will then be displayed on the segment displays.

Hopefully I explained myself correctly.

#### WBahn

Joined Mar 31, 2012
26,398
You are making things more complex than they need to be. You have an adder for the purpose of doing math. So let it do the math!

You have a control signal, call it P, from your pushbutton. If it is a 0 you want to output A and if it is a 1 you want to output -A.

You know that

A = A + 0

and that

-A = (~A) + 1

Where ~A is the bitwise inverse of A.

What gate can you use that will pass a bit unchanged if a second input is a 0 and invert the bit if the second input is a 1?

#### mikez

Joined Jan 21, 2013
47
XOR? I am guessing. Not too sure if I am able to visualize what you are asking.

#### thatoneguy

Joined Feb 19, 2009
6,359
Are you writing this in Verilog, VHDL, Schematic Capture, or <other>?

What are the restrictions for the output to 7 segment?

I'll let WBahn finish his lesson.

#### mikez

Joined Jan 21, 2013
47
Are you writing this in Verilog, VHDL, Schematic Capture, or <other>?

What are the restrictions for the output to 7 segment?

I'll let WBahn finish his lesson.
I am using Xilinx to construct the circuits themselves and then they will be uploaded to the Digilent Basys2 boards for actual physical testing. I believe I have finished the first portion of the assignment, but now I am having to work on the part where I do a 4-bit to 7-bit conversation. I have the truth table set up, but now my restrictions for setting up this circuit is that I may only use SEVEN 8x1 muxes, and 1 inverter to accomplish this. I have another thread going on this topic if maybe you care to take a peek and give some suggestions of advice.

#### WBahn

Joined Mar 31, 2012
26,398
XOR? I am guessing. Not too sure if I am able to visualize what you are asking.
So I have a data input, D, and a control input, C. I want the output, Y, to be equal to D if C=0 and D' if C=1. Capture that in a truth table.

CD|Y
0D|D
1D|D'

Now expand it to a fully enumerated truth table.

CD|Y
00|0
01|1
10|1
11|0

It's the truth table for an XOR. So an XOR can function as a programmable inverter.

See if you can now sketch your entire circuit using just the 8-bit adder and eight of these programmable inverters.

#### WBahn

Joined Mar 31, 2012
26,398
One thing I thought of last night and will throw out for completeness. The notion of using the Enables on the MUXes that was initially discussed would not have worked the way we (or at least I) was envisioning. I was thinking in terms of an Output Enable in which a disabled output is high impedance ('tristated') so that you could directly tie the two MUX outputs together. But I'm willing to bet that when these MUXes are disabled the output is simply forced LO (an active LO) so that the outputs have to be combined using an OR gate, which you did not have in your bag-o-gates.

#### Getts

Joined Apr 12, 2014
10
Alright sorry to pull some necromancy here, but I actually am doing a similar project and have no idea how to get the two's complement. This is what I have so far. Unfortunately the bottom of the picture was cut out, it's just another adder down there.

http://i.imgur.com/EIKc5mT.png

#### Getts

Joined Apr 12, 2014
10
Sorry for the double post, but I got it!

Just took a night of a break, and as soon as I got up I figured it out. Wasn't even that difficult. Thanks!