# Help with a CMOS logic gate circuit

#### raziell122

Joined Mar 28, 2023
52
Hello everybody!
I started working on the following exercise, in the first section they asked me to complete a truth table that contains the working conditions of the transistors, and when I finished my table I saw that the solution for this was different.
I would like to know please how is it possible that Q12 can be 'ON' while Q11 is 'OFF' as the solution shows in the rightmost column.
The circuit:

My table:

The table of the solution:

#### WBahn

Joined Mar 31, 2012
29,519
Keep in mind that tables like these are treating the FETs as simple voltage-controlled switches that are either ON or OFF based on the gate voltage. Whether the source of an NFET is floating or not doesn't matter in terms of the digital functionality.

The state of Q11 is therefore solely dependent on inputs A, B, and C, while the state of Q12 is determined solely by input D.

#### raziell122

Joined Mar 28, 2023
52
Keep in mind that tables like these are treating the FETs as simple voltage-controlled switches that are either ON or OFF based on the gate voltage. Whether the source of an NFET is floating or not doesn't matter in terms of the digital functionality.

The state of Q11 is therefore solely dependent on inputs A, B, and C, while the state of Q12 is determined solely by input D.
Thank you that was very helpful!
What about if it was a TTL circuit? only BJTs.

#### WBahn

Joined Mar 31, 2012
29,519
Thank you that was very helpful!
What about if it was a TTL circuit? only BJTs.
TTL circuits are a bit harder to analyze in detail, but the same basic idea applies. For instance, here's the classic TTL NAND gate:

#### dl324

Joined Mar 30, 2015
16,168
I would like to know please how is it possible that Q12 can be 'ON' while Q11 is 'OFF' as the solution shows in the rightmost column.
Q9-12 form a 2 input NAND gate. The inputs have 4 possible combinations. The state you mentioned is one of them.

#### raziell122

Joined Mar 28, 2023
52
TTL circuits are a bit harder to analyze in detail, but the same basic idea applies. For instance, here's the classic TTL NAND gate:

View attachment 297240
Hey dear friend,
may you help me again please to understand a similar case just in TTL logic? the last explanation of CMOS was very helpful!
I have the following logic gate:

And they are asking me to complete the same truth table.
I created the following table, and the solution one below, I marked with a green color the differences between them.
I just want to know if it is possible that Q4/Q5 will be in SAT mode while Q6 is OFF, just as you told me in CMOS.