Help to design CMOS opamp

Thread Starter

Maryam Zia

Joined Dec 29, 2023
5
Hello,

I am currently working on three stage amplifier design load of 10nF capacitor, and I am asked to find the voltage gain > 80dB, phase margin 60-80deg, power consumption < 130uW, Slew Rate ≥ 4/s and also bandwidth (unity gain) >1.2MHz.
I am getting gain of 50dB and phase margin 91degree, How can I increase my gain and fulfil the above requirement.

1703863332040.png

M1 & M2= 80u/4u
M3 & M4= 70u/0.6u
M5=5u/0.19u
M7=50u/0.19u
M8=1000u/0.18u
M6 & M11=100u/0.18u
M9=200u/0.18u
M10=980u/0.19u
M12=1000u/0.19u
 

WBahn

Joined Mar 31, 2012
30,008
How did you arrive at the design you currently have?

What is the gain you are getting from each stage?

What have you already done to try to improve this?
 

WBahn

Joined Mar 31, 2012
30,008
I'd recommend making the relevant information about the transistors (such as width and length) visible on the schematic. Then place them neatly. Your goal is to make it so that if you print the schematic and hand it to someone, they have all the information they need about the circuit.
 

ericgibbs

Joined Jan 29, 2010
18,826
Hi Maryam.
This simulation is what I see using your circuit.
Note: I have made the .lib local for my PC.
Also added MOS dimensions.

My experience in MOS design is very limited.:(

E
EG57_ 1379.png
 

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Thread Starter

Maryam Zia

Joined Dec 29, 2023
5
Spending entire week on it but can't get the results out of it. I redraw it, change my schematic, ran simulation, did multiple calculations and change the transistor sizing but no matter what I do... I cant get the above parameters
Deadline for my homework is by tomorrow I have to complete it by today
I really need urgent help or clue to complete my homework by today
Thanks in advance for support + consideration
 

WBahn

Joined Mar 31, 2012
30,008
I don't know if you have enough voltage overhead, but have you looked at using a Wilson current mirror as your active load?
 
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