Help please - Class D Amplifier Dead Time

Thread Starter

Lucas Castelan Prado

Joined May 12, 2016
4
Hello everyone.

I am trying to design a Class D amplifier for a subject in college. I used a full bridge topology.

Everything is going as expected, except that i have 120A in my power transistors.

I have researched online and found that i need a dead time circuit, so both transistors don't stay on at the same time.

How can i do that? I can't find the answer online. Can someone please help me?

I have my circuit, and three graphics in attachment (images).
The first is the current in the power mosfet (in blue), the second is the "sound" entering the class D (a sine wave, in green), and the third is the differential output from the class D (in red).

I am simulating it in LTspice

The circuit, from left to right: PWM(comparator) -> level shifter -> buffers -> power mosfets -> low pass filter -> load(speaker)Screen Shot 2016-06-19 at 18.18.00.png Screen Shot 2016-06-19 at 18.22.13.png
 

Alec_t

Joined Sep 17, 2013
11,755
Can you post your .asc file?
Why do you have cascaded push-pull FET pairs, e.g M9-16 ? Is this to generate a delay?
The generic FETS in LTspice don't give realistic responses. Use real FET types.
You can use logic gates and RC time constants to provide deadtime. The gate terminals of the PFETs will need to be driven separately from the gate terminals of the NFETs.
 
Last edited:

Thread Starter

Lucas Castelan Prado

Joined May 12, 2016
4
Can you post your .asc file?
Why do you have cascaded push-pull FET pairs, e.g M9-16 ? Is this to generate a delay?
The generic FETS in LTspice don't give realistic responses. Use real FET types.
You can use logic gates and RC time constants to provide deadtime. The gate terminals of the PFETs will need to be driven separately from the gate terminals of the NFETs.
The .asc file is attached to this reply.

The cascade inverters are to generate enough current to drive the capacitors of the power mosfets.

I have no delay circuit here.

Here, in annex, i am sending you the circuit with two ideal buffers instead of the cascades in the former circuit.

I am using generic fets because i can edit the width and length of each channel.
 

Attachments

Wendy

Joined Mar 24, 2008
22,178
Here is something I drew up several years ago. I never build it, but I address the problem with two separate compactors for each signal feeding a full bridge.

Pwr Class D Amplifier.png
 
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