Hello All,

I'm performing a lab project and I'm trying to figure out what to do with the Wilson current mirror I built. It works find , but I'm not finding many applications. Is there any application that is feasible within a 2 week timespan. I've been searching for hours and I'm not finding anything appropriate. It can be moderately complex, but I'm having trouble generating ideas.

I thought about maybe converting the current source and alternating some charge using a diode. I thought about a feedback loop that I could use for the op amp or maybe a sensor by combining it with a bridge amplifier. Could anyone provide some ideas and some good sources please? I may be looking in the wrong place.

 

You can create a sawtooth oscillator by using the current source to linearly charge a capacitor. Use a comparator that goes high when the voltage across the capacitor reaches a certain point to turn on a transistor to discharge the capacitor (quickly). I have a LTSpice circuit which I can provide once I get home.

 

You can create a sawtooth oscillator by using the current source to linearly charge a capacitor. Use a comparator that goes high when the voltage across the capacitor reaches a certain point to turn on a transistor to discharge the capacitor (quickly). I have a LTSpice circuit which I can provide once I get home.

Thank you for the help. I'll do some research on it, but if you can provide a model, I'd appreciate it.

 

Sorry, I forgot about this yesterday. I used a basic current mirror but a Wilson will do fine too. The NMOS is a subcircuit that's not in the standard LTSpice library, so you'll need to replace it with a standard NMOS.

 

Hello Veracohr,

I opened the file and found a missing piece that looked like it was supposed to be attached to the capacitor. I'm sure that is the NMOS you mentioned, so let me know if this this is correct:
the gate of the NMOS is attached to the capacitor, the source is attached to the 10k resistor, and the drain is attached to the capacitor and 20kohm resistor.

Thank You,
Adam Basha

 

I opened the file and found a missing piece that looked like it was supposed to be attached to the capacitor. I'm sure that is the NMOS you mentioned, so let me know if this this is correct:
the gate of the NMOS is attached to the capacitor, the source is attached to the 10k resistor, and the drain is attached to the capacitor and 20kohm resistor.

The comparator is controlling the MOSFET as a switch so the connections are:
Drain to top of capacitor
Source to bottom of capacitor
Gate to 10k resistor, R6.

 

The comparator is controlling the MOSFET as a switch so the connections are:
Drain to top of capacitor
Source to bottom of capacitor
Gate to 10k resistor, R6.

Right

 

Alright thanks guys!

 

Right

I attempted to analyze the circuit. Please let me know if I'm on the right track:

The current mirror creates a constant current through C1 to charge the capacitor. The voltage on the bottom of the capacitor should be the same as the voltage at the negative node which should in turn be the same as the voltage of the positive node. The op amp acts like a non-inverting operational amplifier but no current goes through the gate. I'm not sure if the NMOS is in triode mode or saturation mode, but I assumed saturation. Next the charge of the capacitor dictates the power of the op amp and when it reaches saturation the opamp stops the current flow and he capacitor discharges linearly? But it would only discharge linearly if the discharge wasn't complete since the discharge itself is exponential. Please let me know if I'm making sense or if I need to rethink my logic.

You guys are the best and thanks a bunch!!!

 

Not sure if your explanation is totally correct. At the end of the ramp the MOSFET is turned on as a switch and rapidly discharges the capacitor to a low voltage (approximately equal to the MOSFET's threshold voltage). The current-mirror then linearly charges the capacitor by drawing a constant-current from the bottom of the capacitor, generating a negative linear slope at Vout. At the bottom of the ramp the output of the comparator (not an op amp) goes high to again rapidly discharge the capacitor.

 

Not sure if your explanation is correct. At the end of the ramp the MOSFET is turned on as a switch and rapidly discharges the capacitor to a low voltage (approximately equal to the MOSFET's threshold voltage). The current-mirror then linearly charges the capacitor by drawing a constant-current from the bottom of the capacitor, generating a negative linear slope at Vout. At the bottom of the ramp the output of the comparator (not an op amp) goes high to again rapidly discharge the capacitor.

Alright I think I got it. Thanks.

 

Wait

Alright I think I got it. Thanks.

Wait when you say the MOSFET is turned on, are you talking about triode mode or saturation mode?

 

Wait

Wait when you say the MOSFET is turned on, are you talking about triode mode or saturation mode?

If the Vcc value above the capacitor is constant then the voltage below it must decrease to charge the capacitor, but how can it discharge when there is a constant current going through it. I know the opamp sets the gate voltage to about 2.45V. So when the source voltage is low enough the NMOS goes to cutoff mode and the current must discharge in the opposite direction through the current source, until the source voltage is high enough to allow current through the NMOS. Then the current charges the capacitor again in the opposite direction. I think that is how your producing the linear wave. Wait then the NMOS takes all the current from the current source while the capacitor discharges since the capacitor becomes an open circuit. I just don't see how you can connect a capacitor to a current source. Could you please explain it to me.

 

Consider the capacitor equation I=C*dV/dt. You have a current source, so I is constant; you know C is constant; so dV/dt is the only thing that can change. In a simple RC circuit, I goes down as the capacitor charges and that's why you get a logarithmic charging curve. But with a constant current source I won't change, so dV/dt stays constant, which is how you get the linear ramp. Because the mirror is a current sink and the top of the capacitor is held constant at Vcc, that means the bottom side of the capacitor must lower in voltage as the capacitor is charged. No current goes through a capacitor; the current sink just causes the charge on the bottom side of the capacitor to become more negative with respect to the top side. As in: there are more electrons on the bottom plate than on the top.

Just think of the MOSFET as a switch. It's either off, and might as well not be there, or it's on and looks like a wire across the capacitor.

 

Consider the capacitor equation I=C*dV/dt. You have a current source, so I is constant; you know C is constant; so dV/dt is the only thing that can change. In a simple RC circuit, I goes down as the capacitor charges and that's why you get a logarithmic charging curve. But with a constant current source I won't change, so dV/dt stays constant, which is how you get the linear ramp. Because the mirror is a current sink and the top of the capacitor is held constant at Vcc, that means the bottom side of the capacitor must lower in voltage as the capacitor is charged. No current goes through a capacitor; the current sink just causes the charge on the bottom side of the capacitor to become more negative with respect to the top side. As in: there are more electrons on the bottom plate than on the top.

Just think of the MOSFET as a switch. It's either off, and might as well not be there, or it's on and looks like a wire across the capacitor.

Alright that helps a lot. My last question is how can the capacitor discharge if Vcc is constant. If the capacitor is discharging, its no longer drawing power from Vcc and has to discharge through the NMOS, but how is that possible if the current mirror is still connected? I understand the main idea, but I still don't understand how the current mirror will let the capacitor discharge in the opposite direction to the NMOS. the current would have to flow from source to drain not drain to source.

 

Because Vout, the bottom of the capacitor, is not constant. The capacitor isn't drawing power, it just happens to be connected to Vcc because that pins one side of it to a constant voltage. If you made a PNP current mirror (sourcing current), you would connect that side of the capacitor to ground and the voltage across the capacitor would rise instead of fall.

When the switch is on the current mirror is still doing its thing, it's just now drawing current from Vcc through the MOSFET instead of from the capacitor. The current mirror can still sink its current, but the voltage at that point can go back up as the capacitor discharges through the MOSFET. In the file I attached, the current source is pulling 66μA, but the capacitor discharge current peaks at 1.3A. The 66μA from the current mirror is part of that, it's just completely dominated by the discharge current.

That's an important consideration if you plan to build this circuit. I put in the model of MOSFET I happen to have so I could make sure the discharge current remains in the safe operating area, because for my purposes I wanted no more than 1μs discharge time but I had to make sure I wouldn't burn up the FET. You can reduce the peak current by introducing some extra resistance between the capacitor and the MOSFET, which will also extend the discharge time.

 

Because Vout, the bottom of the capacitor, is not constant. The capacitor isn't drawing power, it just happens to be connected to Vcc because that pins one side of it to a constant voltage. If you made a PNP current mirror (sourcing current), you would connect that side of the capacitor to ground and the voltage across the capacitor would rise instead of fall.

When the switch is on the current mirror is still doing its thing, it's just now drawing current from Vcc through the MOSFET instead of from the capacitor. The current mirror can still sink its current, but the voltage at that point can go back up as the capacitor discharges through the MOSFET. In the file I attached, the current source is pulling 66μA, but the capacitor discharge current peaks at 1.3A. The 66μA from the current mirror is part of that, it's just completely dominated by the discharge current.

That's an important consideration if you plan to build this circuit. I put in the model of MOSFET I happen to have so I could make sure the discharge current remains in the safe operating area, because for my purposes I wanted no more than 1μs discharge time but I had to make sure I wouldn't burn up the FET. You can reduce the peak current by introducing some extra resistance between the capacitor and the MOSFET, which will also extend the discharge time.

Alright I need Beta for each transistor, the kn*W/L value that you used. If Vsource is going down then VGS is going up but the drain is attached to 9V which is much higher than the 2.45 V gate meaning the NMOS is active in saturation mode and inactive in cutoff mode. Is that right? Because I'm going to use the saturation equation Id=1/2*kn*W/L*(VGS-Vt)^2 to find the maximum current through the capacitor which I assume occurs right when the MOSFET reaches saturation. I need to analyze this circuit comprehensively. I need this kind of detail. I understand the main idea, but I need equations, not just a conceptual understanding. I appreciate the responses you've given so far, but could you please answer my question with this kind of detail?

Thanks Again

 

Well at that point you're just asking me to do your homework for you. If you need to present a detailed analysis of a circuit, and you can't do so sufficiently for this circuit with your current knowledge, maybe you should go with a simpler one. If you'd said you had to present such a detailed analysis I probably wouldn't have suggested it, or even gone this far in explaining it.

Beta for the BJT models I used is a widely quoted number, which also happens to vary widely, and is why people generally like to build circuits that don't depend on Beta. It also doesn't matter that much. Run the simulation with a modified Beta for the transistors and you'll see that it doesn't really matter (in simulation anyway).

I think you need to review your MOSFET knowledge; the transistor is only on when Vgs becomes greater than the threshold voltage, regardless of Vds. Once Vgs>Vthreshold, only then does Vds determine whether it's in saturation or triode mode. In the MOSFET I used Vt is about 1V, but Vt varies greatly from one model to the next. As for figures like Kn, Width, and Length, you can find those in the SPICE models, and Vt is in the SPICE model as well as the datasheets.

There's more I could explain, especially regarding the maximum discharge current, but I think it would just confuse the issue and make things harder for you. Maybe you'd be better off just removing the MOSFET and comparator parts and present the current sink/capacitor as a linear ramp circuit (without discharge). Or if you really wanted to calculate the maximum Id, just use the maximum voltage across the capacitor and the minimum Ron of the transistor, which is in any datasheet. You'll get a higher number than reality because Id will rise and fall at a slope, not instantaneously, but I don't know what your requirements are.

 

Well at that point you're just asking me to do your homework for you. If you need to present a detailed analysis of a circuit, and you can't do so sufficiently for this circuit with your current knowledge, maybe you should go with a simpler one. If you'd said you had to present such a detailed analysis I probably wouldn't have suggested it, or even gone this far in explaining it.

Beta for the BJT models I used is a widely quoted number, which also happens to vary widely, and is why people generally like to build circuits that don't depend on Beta. It also doesn't matter that much. Run the simulation with a modified Beta for the transistors and you'll see that it doesn't really matter (in simulation anyway).

I think you need to review your MOSFET knowledge; the transistor is only on when Vgs becomes greater than the threshold voltage, regardless of Vds. Once Vgs>Vthreshold, only then does Vds determine whether it's in saturation or triode mode. In the MOSFET I used Vt is about 1V, but Vt varies greatly from one model to the next. As for figures like Kn, Width, and Length, you can find those in the SPICE models, and Vt is in the SPICE model as well as the datasheets.

There's more I could explain, especially regarding the maximum discharge current, but I think it would just confuse the issue and make things harder for you. Maybe you'd be better off just removing the MOSFET and comparator parts and present the current sink/capacitor as a linear ramp circuit (without discharge). Or if you really wanted to calculate the maximum Id, just use the maximum voltage across the capacitor and the minimum Ron of the transistor, which is in any datasheet. You'll get a higher number than reality because Id will rise and fall at a slope, not instantaneously, but I don't know what your requirements are.

I'm not asking you to do my homework. I tried to analyze it for hours and couldn't do it. I don't have all the time in the world. That's why I'm asking for help. I'll check the datasheets no problem. The main problem is finding the maximum voltage of the capacitor. Because the NMOS is on anyway when VGS>Vt, so the maximum charge of the capacitor must be 9-1.45V=7.55V before discharge. I should've known that the Beta for a MOSFET is infinity since no current flows through the gate, but please let me know if I at least have this correct.

 

The maximum voltage on the capacitor is determined by the comparator. I don't know where you got 1.45 from, but there are 3 resistors on the comparator that determine when it goes high and turns on the MOSFET, and that determines the maximum capacitor voltage. 1.45 isn't it, but it should be easy to figure out.

Beta is a parameter only BJTs have, not MOSFETs. Beta is current gain, and you can't have current gain when there is no input current.