It seems obvious that the Output is a gated Clock signal. So what does the gating signal need to look like? How would you generate such a signal? Depending on the level of sophistication required, you may need to consider race conditions & transient glitches in the Output. Would the gating signal need to change state on the rising or falling edge of the Clock?May be it need divide by 3 circuit,
If you need it ASAP, then you better hurry up and make some attempt to come up with a logic circuit so that we have a starting point to help guide you along. We are NOT going to do YOUR homework for you.i am beginer level in binary/digital circuit design. i build clock with ne555 ic. it work at low level frequency, 3hz. it call 2/3 clock ratio, 1 1 and the last one is 0. i need asap (as simple as posible) circuit after my 555 low frequency oscilator.
by Duane Benson
by Jake Hertz
by Duane Benson
by Jake Hertz