Hi all

I would like to do a frequency multiplier synchronized to the frequency of the mains (i.e. 50Hz)

I am using an old(but gold) HCF4046, I have read several data sheets, application notes but I am still stuck.

Here are the parameter

R1 = 10kOhm
C1 = 2.2nF
Vcc = 5V
-Vcc = -5V

so the central frequency is around 20kHz

I am using a divider between VCOout - COMPARATORin, a HEF4040, for now just to divide by 256.

I am using Phase Comparator 2 and between PhaseCompIIout and VCOin I have an active loop filter:



The problem is that no matter the filter I am using (tried also a lead-lag passive filter) the output frequency is not stable at 12800Hz but it somehow oscillates and the most surprising fact is that with the passive filter it had an oscillation of around +-2Hz around 12800Hz while with the active filter it is even worse.

It's a long time and finally I decided to ask for some help, have you any suggestion/hints?

 

Hello,

When multiplying a frequency, the variations on the reference frequency will also be multiplied by the same factor.
How is the complete PLL circuit build?
Do you have a complete schematic?

Did you have a look at the synthesizer schematic on page 19 pf the datasheet?

Bertus

 

Hello,

When multiplying a frequency, the variations on the reference frequency will also be multiplied by the same factor.
How is the complete PLL circuit build?
Do you have a complete schematic?

Bertus

Actually I do not have the complete schematic, but basically I have a passband filter (MAX267) that goes in a diode then in a Schmitt Trigger (74HCT132), finally, in the 4046.
The opamps for the loop filter are not OP27 but LM324N.
I have checked the signal given as an input to the 4046 it is stable with a duty cycle 51% Ton 49% Toff

 

If it is useful I can draw the whole schematic

Edit. Yes I followed the schematic of that application note and I decided to switch to an active filter rather than a passive one because of the +-2Hz oscillations in the output frequency (even if that led only to greater oscillations)

 

Hello,

Did you use the schematic for the synthesizer in the datasheet?



The divider in your case is the 4040.

Bertus

 

Hello,

Did you use the schematic for the synthesizer in the datasheet?

View attachment 112772

The divider in your case is the 4040.

Bertus

Yes I took this schematic as reference (with different divider) and I aldo changed the loop filter to have a good attenuation at 50Hz, the one in the schematic has 100Hz cutoff frequency which is good for 1kHz but not for my case

 

Your loop filter lacks the lead-lag characteristics for solid lock, it's "hunting".

Note R4 in the simple example, this allows some of the phase detector signal to go through without phase shift, this allows it to lock.

 

Your loop filter lacks the lead-lag characteristics for solid lock, it's "hunting".

Note R4 in the simple example, this allows some of the phase detector signal to go through without phase shift, this allows it to lock.

Ok I understand, so a topology like an active lag filter should work fine? What do you think is better between this two filters the first one is faster but with less attenuation on the 50Hz the other one pays the attenuation in terms of speed



EDIT. Could you give me some reference for better understand why a lead-lag filter is necessary for having the PLL locking and not going nuts going hunting?

 

I would ditch all those extra parts and go with the simple filter in the data sheet.

Thinking the main job of the filter is to "attenuate the 50 Hz" is not correct, you are going to drive yourself nuts adding all this unnecessary complexity.

 

I would ditch all those extra parts and go with the simple filter in the data sheet.

Thinking the main job of the filter is to "attenuate the 50 Hz" is not correct, you are going to drive yourself nuts adding all this unnecessary complexity.

If not for this reason how would you choose your cutoff frequency?

 

if you are building a frequency synthesizer, the loop filter time constant determines the agility of changing frequency, so the time constant could be seconds.

I suggest building a breadboard of the simple filter, with pots in place of the resistors, play with it to get an intuitive feel for what's going on.

Then read the data sheet and do the painful math to select the components.

 

At lock, the phase comparator 2 output is in the open circuit state and the VCO control voltage is held substantially constant by the capacitor of the simple low-pass filter shown in the datasheet for the CD4046. Your more complex filter circuit has no such capacitor. I think when the filter circuit input is open-circuited the opamp U2 output will not be held at the required level but instead will be determined by the opamp bias conditions (offset etc), leading to a frequency offset.

 

Below is an LTspice simulation of a CD4046 with a CD4040 in a divide by 256 configuration between the VCO output and the comparator input, and a simple RC loop filter on the PC2 output.
(I used this CD4046 model.)
R2 provides some lead compensation to prevent overshoot and hunting.
As you can see, the loop appears stable after about 1.3s from the simulation start.
[V(p001) is the voltage on the loop filter cap, C3].
At that point the VCO output is a steady 12.8kHz.

 

Below is an LTspice simulation of a CD4046 with a CD4040 in a divide by 256 configuration between the VCO output and the comparator input, and a simple RC loop filter on the PC2 output.
(I used this CD4046 model.)
R2 provides some lead compensation to prevent overshoot and hunting.
As you can see, the loop appears stable after about 1.3s from the simulation start.
[V(p001) is the voltage on the loop filter cap, C3].
At that point the VCO output is a steady 12.8kHz.

View attachment 112809

Thanks for the help.
Your LPF is quite close to the passive filter I designed:


So the problem must be in R1, C1. Here is the graph with your LPF and my R1, C1:
as you can see it cannot reach a steady state



While if I keep my LPF (which I thought was the cause of the oscillations) but with your new values for R1 C1:
it seems good, rougly the same as yours



The problem now:
I am quite confused, how did you choose R1 and C1?
You didn't use the graph in the data sheet, but I thought that R1 C1 were not such critical components for the correct operation of the PLL and so the difference between mine and yours not a big issue.

I have chosen fo = 20kHz and R1 C1 such that the PLL could work in a range 0 - 40kHz (so that I could change the divider from 128 - 512 without changing R1, C1).
I am missing something but where?

 

I'm not sure why the data sheet values don't seem to work.
I just adjusted the values until the simulation was stable.
For example if you set R2 to 50k and C3 to 2μF (in my schematic), the loop also is stable, with step response of about 400ms.
A larger time-constant usually works fine. It just makes the step response at start-up or with a change in divider ratio longer.
So if you can tolerate a longer step response, you can use a larger time-constant to help insure stability.

To speed the simulation I take the counter out of the loop and increase the value of C1 by a factor of 256.
The loop dynamics are essentially the same and the simulation is much faster without the counter in the loop.

 

Fig 4 of the Texas Instrument Application Note SCHA002A - February 2003, together with Fig 9a, give component selection guidance.
The following approximation from theoretical considerations may be useful -
f0 = (Vdd/2 - 1)/((Vdd + 1.2) x R1 x C1)

 

Again the output is not stable:

I have changed values to the one proposed by crutschow.

 

8.2k is below the minimum recommended value (10k) for R1.
What is the time constant of your LPF?

 

What is your trigger signal for the oscilloscope?

 

What is your trigger signal for the oscilloscope?

The rising slope of the output clock itself, should be stable