Hi guys,

I've been given the task to design a multistage transistor amp. Specs given are:
Overall voltage gain: 80 (min) to 100 (max),
Input resistance no less than 1Mohm,
Voltage supplies: +-10V,
Achieve max output voltage swing when Load Resistance is 2kohm,
Capacitive coupling with low freq cut off of no lower than 30Hz but no greater than 60Hz,
Amp must also include negative feedback from final stage to an earlier stage (preference: voltage-voltage/voltage-series).

I have decided on 3 stages, with the input stage being a JFET (Common Source), and the others BJTs. Currently, I am trying to choose the gain of each stage and design as single stage amplifiers:

Stage 1 (JFET-2N3819): Gain = 2 (high input resistance + moderate voltage gain)
Stage 2 (BJT): Gain = 30 (high gain)
Stage 3 (BJT): Gain = 2 (low output resistance + buffer high gain stage; hoping overall gain will reduce to given range above when negative feedback is introduced)

My problem here is I don't know how to tackle such a task. For example, in the input stage, I'm unable to calculate values of my resistors (R1, R2 in voltage divider, RS, and RD), and associated caps for coupling/bypass. I have tried working out small-signal models as well, but to no avail.

Help much appreciated!

 

First try to show us a full circuit diagram.

 

I offer another amplifier structure. ComDrain+ComEmitter+ComCollector.
Adjust the gain makes the feedback resistor R7. The lower frequency is determined by a capacitor C3.
The remaining capacitors provide substantially cutoff frequency below 30 Hz.
See

 

I have been taught that in a multistage design, you start at the output (last stage) and work your way to the input. If you do three stage design, then you know parameters of your third stage, design it and use values of the third stage as output of the second stage and so on.

 

First try to show us a full circuit diagram.

Thanks for the reply! I'm not sure on how I will design all stages and include negative feedback, but I've settled on using a Common Source JFET Amp as my first stage. Have a look at the attachment/uploaded image!

I offer another amplifier structure. ComDrain+ComEmitter+ComCollector.
Adjust the gain makes the feedback resistor R7. The lower frequency is determined by a capacitor C3.
The remaining capacitors provide substantially cutoff frequency below 30 Hz.
See

View attachment 101803

Thank you so much Bordodynov for your reply. I really appreciate the solution, but I really want to learn how to work out those values for resistors/caps, and understand small signal models with such a task at hand. Any ideas on how to tackle this stage by stage? I will also be simulating this in pSpice before (if that helps).

I have been taught that in a multistage design, you start at the output (last stage) and work your way to the input. If you do three stage design, then you know parameters of your third stage, design it and use values of the third stage as output of the second stage and so on.

Thanks shteii01 for the reply. I will try to implement this.

 

Thanks for the reply! I'm not sure on how I will design all stages and include negative feedback, but I've settled on using a Common Source JFET Amp as my first stage. Have a look at the attachment/uploaded image!

In this case try read this
http://forum.allaboutcircuits.com/threads/jfet-amplifier.44328/#post-287187

 

In this case try read this
http://forum.allaboutcircuits.com/threads/jfet-amplifier.44328/#post-287187

In this case, the values for IDSS and VGSoff are known to your man. I don't have these values yet. I know they are not the same for all JFETs/transistors. Am I supposed to assume values?

Thanks,
Raj

 

The Idss and Vgs(off) can be found in transistor data sheet
http://www.onsemi.com/pub_link/Collateral/2N3819-D.PDF
http://forum.allaboutcircuits.com/threads/jfet-load-line-arithmetic.117308/#post-920376
http://cecs.wright.edu/~dkender/bme3512/BiasingFETs.pdf
And some info about BJT amplifiers.
http://people.uwplatt.edu/~drury/bjt_bias.pdf
http://www.zen22142.zen.co.uk/Design/bjtbias.htm

 

The Idss and Vgs(off) can be found in transistor data sheet
http://www.onsemi.com/pub_link/Collateral/2N3819-D.PDF
http://forum.allaboutcircuits.com/threads/jfet-load-line-arithmetic.117308/#post-920376
http://cecs.wright.edu/~dkender/bme3512/BiasingFETs.pdf
And some info about BJT amplifiers.
http://people.uwplatt.edu/~drury/bjt_bias.pdf
http://www.zen22142.zen.co.uk/Design/bjtbias.htm

From the data sheet, I see the typical values for IDSS and VGSoff are 10mA and -8V (Although in the lab, actual VGSoff seemed to be = -4V). Keeping this in mind, I calculated values of resistors:
Assuming RD = 4.5k and RL=10k, I calculated RS = 350ohm. This didnt seem to work in simulation in PSpice or when I built it in the lab. Is there a way to calculate RD/RL instead of assuming values?
However, I have a question regarding biasing in my case. I went with R1=R2=2Meg (for low freq response). Still didn't work.
Which, from Self-Bias and Voltage divider at gate, seems like the best way to go in my design?
Thanks.
-R

EDIT: I cant find min/max values for Vp and Id in the spec sheet. How do I use your/datasheet info to calculate my values?

 

Ok guys, have a circuit diagram of what I want my circuit to look like - each stage with gain hoping to be achieved. Apologies for the hand drawn circuit; I currently dont have a working simulator on my laptop (LTSpice/PSpice none worked for me).
Can someone help me with the values of the resistors and capacitors?
Also, I'm not sure how I will implement voltage-voltage/voltage-source feedback, but at the moment, I'd like the circuit to work in the manner/build as described in the attached photo.

Thanks again guys! Much appreciated

 

Can someone help me with the values of the resistors and capacitors?

How is that (help) to be "implemented" in practice?
Also you do not need CE and CS capacitors for such a low gain in the individual stages.

 

Ok guys, have a circuit diagram of what I want my circuit to look like - each stage with gain hoping to be achieved. Apologies for the hand drawn circuit; I currently dont have a working simulator on my laptop (LTSpice/PSpice none worked for me).
Can someone help me with the values of the resistors and capacitors?
Also, I'm not sure how I will implement voltage-voltage/voltage-source feedback, but at the moment, I'd like the circuit to work in the manner/build as described in the attached photo.

Thanks again guys! Much appreciated

lol
if I calculate all those things, then why do I need you?

 

I'm hoping to go into the lab and build this.
I tried simulating the first/JFET stage in PSpice with the values calculated for resistors and caps assuming VGSoff = -8V and IDSS = 10mA (from 2N3819 data sheet), but didn't provide the gain I hoped it to.
Hence, I'm asking for help here. Even if I get values, I could calculate backwards and see how the theory works out.

Again, much appreciated.
-R

 

Try measure Idss and Vgs(off) in simulator or find this in Pspice lib.

 

See circuit.
Such a structure is preferable. I'm not picking up the capacitor so that fulfill your requirements.
I am using LTspice. This program is available for free and has no restrictions on the value of circuits.

 

Hi Bordodynov,

I tried using your configuration today in the lab, and achieved a gain of about 73 (87 in the Simetrix simulator).

I offer another amplifier structure. ComDrain+ComEmitter+ComCollector.
Adjust the gain makes the feedback resistor R7. The lower frequency is determined by a capacitor C3.
The remaining capacitors provide substantially cutoff frequency below 30 Hz.
See

View attachment 101803

I took C3 = 100u and R7 = 10.
My question for you is how do I implement negative feedback from the output of stage 3 to stage 2?
I did some reading around, and it seems like I should split the emitter resistors in Stage 3 like you did in Stage 2, but in series. And, I should take my output (before cap C4 in Stage 3) and connect it to the emitter of Stage 2 before the resistor split, AND ALSO introduce a collector resistor in Stage 3. My overall gain should get reduced due to this feedback.

Am I on the right track?

Thanks
-R

 

Raj Shah.
A=Aj1*Aq1*Aq2=0.75*7*60=315>100 without feedback.
Feedback reduces the gain to an appropriate level. Also, the feedback reduces the output impedance of the amplifier, which is good. Also reduces distortion.
I do not understand what you want to do with the scheme. It would be better to give you a picture. But even then my circuit fulfills your requirements.

 

This photo attached shows the feedback I am trying to implement. Any advice on this? The task requires me to take feedback from third stage output to an earlier stage (stage 2 most likely).

Thanks,
-R

 

What would be a stock gain without feedback does not need to put in the emitter of the second bipolar transistor, two resistors. To obtain a sufficiently large gain without feedback you need to use transistors with a large beta.For example BC547C.
Using its experience and LTspice program, I got the values of resistors and capacitors. I got a gain of 94 and a lower cut-off frequency of 30 Hertz. But I do not put on a review of the scheme, because in this forum do not approve of it. Calculate the resistor values analytically possible, but difficult. It should be a lot of equations.

 

Well guys, I appreciate the help. This circuit worked, and I was able to achieve the spec.
However, I've now been instructed to design the same multistage amplifier within the same specs using the scheme in the attached photo. Any help there with resistor/cap values is much appreciated! (Note: R10 is my feedback resistor)

Thanks,
-R