1. a) The first access to any cache block/page results in a miss, and called "compulsory misses' - "these are truely compulsory only if we follow on-demand fetching" - Explain.
b) A program accesses each element of a 1024X1024 matrix 8 times in each course of its execution. If the data cache can accommodate 256 matrix elements and 16 matrix elements per block/page, then how many compulsory data cache misses will be caused by this program's execution ?

2.Illustrate the 'diagonal format of encoding micro-instructions for a micro-programmed control unit with an example. Find out the cost optimal micro-instruction format for a system with the following set of micro-instructions and controls. Ensure minimum length of the micro-instruction format as well as the maximum parallelism among the micro-operations.

Microinstructions Control signals
I1 b, e, f
I2 a, b, c, d
I3 a, b, e, h
I4 b, e, g

3.A m/c is being designed whose instructions range from 1 to 6 bytes in width, with 2-bytes instruction being most common and 5- or 6-byte instruction rarely used. Compare the following opcode encoding schemes-
i. The leftmost 3 bits in the first byte of every instruction contains a binary number (1 to 6) that indicates the width of the instruction in bytes.
ii. One-byte instructions begin with 0 in the leftmost bit position of the first byte, 2-byte instructions begins with 10, and all other instructions begin with 11 followed by a 2- bit field that indicates the number of additional bytes (beyond the third) in the instruction.

 

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1. A program accesses each element of a 1024X1024 matrix 8 times in each course of its execution. If the data cache can accommodate 256 matrix elements and 16 matrix elements per block/page, then how many compulsory data cache misses will be caused by this program's execution ?

Ans: Now , I have assumed the following things:-
i) The Main memory size is 1024X1024Xsizeof(int).
ii) The number of blocks in cache is= 256/16=16.
iii) The access is row-wise means
array[0][0],[0][1],…[0][1023]
[1][0],[1][1],…[1][1023]
……
[1023][0]……….[1023][1023] are accesed sequentially one after another.
iv) 8 acceses are also sequential:- means first all the elements are accessed one time then again accessed,again,…until the number of access is 8.
v) Also I have considered that the scheme for mapping is “Direct Mapping.
Now ,there are 256/16=16 cache line.Each contain 16 array elements.[numbered 0,1 ,2 ,3,4 ,… ,15].
There are (1024X1024)/16 =65536 main memory blocks.[ block number is 0,1,2,,3,4,……..65535.]
First time [0][0] element will not be there in cache.The whole line of MM numbered 0 will be fethed in cache 0 line. There will be no miss for next 15 elements as they are already in cache.
In 16 elements there are 1 cache miss. There are 16 misses in accesing 256 array elements. There are 1024X1024 elements accessed at a time. There are (1024X1024/256)=4096 cache misses.
The number of misses in 1 whole access of 1024X1024 elements is 4096.
For 8 whole access ccache miss=8X4096=32768.
Now Is my answer correct? Please help if there is anything wrong. I will be satisfied if one can give a better solution with a different approach.