Hi All,

What would occur if you exceeded the Vcc requirements for a PIC on the Digital I/O ? (TTL input levels and full CMOS output drivers)

The datasheet says the following - would this prevent the device from getting damaged if say 8/9V was sent to a pin rather than keeping it below Vcc?

 

Why test fate? Go to the Electrical Specifications section of the DS. For 5V devices, it is VDD+0.3V (5.5 V max).

 

5.5V is quoted here alright - thanks for the feedback

Like all Microchip PIC18 devices, members of the PIC18F8722 family are available as both standard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F6627), accommodate an operating VDD range of 4.2V to 5.5V. Low-voltage parts, designated by “LF” (such as PIC18LF6627), function over an extended VDD range of 2.0V to 5.5V.

 

In general, you can safely go below Vss or above Vdd in voltage, provided the current is limited. Once you get beyond the rails by more than about half a volt, the protection diodes will begin to conduct significant current. By 0.7 V or so the current could easily be destructive if not limited.

You will have to refer to the datasheet for the particular part in question because there are so many "technology" variants of PICs. Usually the maximum current is clearly specified, but not always. Values in the range of 2 mA to 40 mA are not unusual. 20 mA is fairly common. However, these are absolute maximum currents. You should stay well away from the absolute maximum - I'd suggest no more than 25-30% if the duration of the event is long or frequent. You must also consider the fact that if you make the diode to Vdd conduct, the current has to go "somewhere" and it can push the Vdd rail excessively high. For example, if you have very little loading the supply rail and put the PIC into sleep mode, you might push Vdd well above the absolute maximum with even tens to hundreds of microamperes. This is also true if you use external protection diodes to clamp a signal to the rail.

±20 mA for the part in question - see Output clamp current, pg 375 of the datasheet

Just because you protect an input from damage does not assure that everything will work properly. This is especially true of analog inputs and with multiplexed inputs one that is beyond the supply rail can cause error in all.

Zeners don't work very well for clamping low voltages because low voltage zeners start conducting well below their nominal voltage.

Sometimes you must use methods such as a zener to reduce the voltage to near the supply rail then another series resistor to limit the current into a pin. Using discrete transistors for level shifters is more complex but also more foolproof in difficult circumstances. Transistor arrays can be useful. (e.g. an common emitter or common source inverter can be scaled to handle "any" input voltage with proper resistor selection). In some cases optocouplers can be useful, but that is a space and money consumptive approach that needs to be considered carefully. Of course spending an extra 50 cents on a board to help assure against $5000 of down-time in a system is generally worth it.

The best general discusssion I've seen is from Nexperia/NXP for their automotive processors. Search for "current injection" with NXP or Nexperia, etc. in the search terms.

 

should have mentioned:

Even if you could find a "perfect" zener that would limit the signal to say 4.5 V, you would still have to consider the case when the power to the processor is turned off. If you don't have additional current limiting resistance between the zener and the input, you could still very easily exceed the maximum allowable current for the protection diode in the processor.

 

I used a PIC in an application which fed a negative voltage to a pin with a resistor to limit the current well below the limit. It didn't damage the PIC but the internal oscillator was very messed up while that negative voltage was present. Major redesign required.

 

A good rule to follow is: do not exceed absolute maximum ratings. For PIC I/O pins, that is 0.3
V above Vdd. Don't exceed that. If you apply a stiff 8 or 9V, I guarantee you will damage the PIC.

Bob

 

I used a PIC in an application which fed a negative voltage to a pin with a resistor to limit the current well below the limit. It didn't damage the PIC but the internal oscillator was very messed up while that negative voltage was present. Major redesign required.

I found out the hard way that forward biasing either of the protection diodes on any analog input pin-- even with a small amount of current-- can cause ADC conversion errors on the other analog input pins. The best policy, I decided, was to ensure ALL pins on the device are kept between Vss and Vdd at ALL times, no matter what.

 

thanks guys, as every some insightful information.

How can I find current limits for the 18f8527, the design I am looking at has no more than some voltage dividers going to the PIC which will be interpreted as a logic low or high, In the example below 6V will be at RF1 but I have seen instances of 8.5V been present on other pins, hence the topic

 

How can I find current limits for the 18f8527...

All of that information is in the data sheet, in the Electrical Characteristics section. Read the data sheet.

 

thanks guys, as every some insightful information.

How can I find current limits for the 18f8527, the design I am looking at has no more than some voltage dividers going to the PIC which will be interpreted as a logic low or high, In the example below 6V will be at RF1 but I have seen instances of 8.5V been present on other pins, hence the topic

View attachment 165073

Be aware of the difference between CMOS and TTL voltage differences. The chips I use default to TTL, which is not usually a problem, even when using level shifters to 3.3 V.

"Study" the datasheet.

 

"Study" the datasheet.

Good advice for EVERY component you use, especially ICs-- not just PICs. Doing so will save you a lot of grief and help you avoid costly-- or even catastrophic-- mistakes.

 

From my previous post:
±20 mA for the part in question - see Output clamp current, pg 375 of the datasheet

If there has actually been 8.5 V on pins, measured relative the the processors Vss pin, then it has survived only by good luck. You cannot get a pin to a voltage that high unless Vdd for the processor has been pushed to something over 7.5 V which is likely well above the absolute maximum for the part.

I've never noticed a spec for such on any PIC I've used, but you do occasionally encounter inputs or outputs that are tolerant of voltage well beyond the supply rails for the part. This is not at all common.

Sometimes you can do things like use an inexpensive non-inverting CMOS hex buffer or the like between signals and the processor. They have similar input protection diodes and you won't scramble other "channels" if the diodes for one are conducting. You still have the issue of forcing Vdd too high.
Schmitt trigger gates and inverters (not much in non-inverting types) are available, and sometimes quite convenient.

Not applicable for digital inputs, but I started writing this before noticing you are dealing with digital inputs only, so it might as well stay:
If you are dealing with analog inputs that may have overvoltage applied, it is sometimes reasonably easily handled by using a unity gain op-amp buffer with a rail-to-rail amplifier powered with the same supply voltage as the processor (or sometime via an RC filter if there is a noise issue). The amp's input can be protected by series resistance and you don't run into problems with corrupting other analog channels (check the specs of dual and quad amps carefully; use singles if in doubt). This is not without problems because such an amp is never able to swing fully to the rails - only to within millivolts. Often voltages near zero are the problem and adding a resistor from the output of the amp to ground forces the amp to always source current and usually gets it down to zero - BUT it wastes power and compromises the ability to get to the positive rail. If a processor or ADC is powered with 5 V, using a 4.096 V reference can make managing some of these problems easier than using a 5 V reference, without being a large compromise in terms of signal to noise & error ratio. Sometimes adding an offset to signals so they might swing from 50 mV to 4 V instead of from 0 V to 4 V can be useful (null the offset in code), but it does add complexity.

 

Hi all,

I have looked at most of the stressed pins going to the PIC, so as you can see 2 of the ADC pins and 3 of the Digital IO look to be over loaded with volts but the current is quite low, there is no reference voltage on this. Would the high voltage listed here kill this pic or would the protection on the PIC prevent failure? will the high voltage be clamped @ 5.3V?

6.06v @ 606uA > ADC input

6.06v @ 606uA > ADC input

8.50v @ 3.15mA > Digital I/O (input)

8.50v @ 3.15mA > Digital I/O (input)

8.50v @ 3.15mA > Digital I/O (input)

Also - I also may have the same issue with this logic buffer - 74HCT244

Is the maximum input voltage 5.5 with a 20mA current clamp also?

https://assets.nexperia.com/documents/data-sheet/74HC_HCT244.pdf

regards.

 

Those voltages could be destructive and mitigation measures are a must!

7.5 V as the absolute maximum for VDD relative to VSS is actually unusually "generous" - many devices that are intended for 5 V max operating VDD allow no more than about 6.5 V absolute max. The processor may have been designed with the intent that it might be operated from a nominally 6 volt battery (e.g. four "alkaline' cells or the like). Usually there is some margin between the specified absolute maximum and the voltage at which the smoke is released, but you are not entitled to assume that and to do so would be very bad design.

When you have one or more of the digital inputs over-driven, check the voltage at the positive power supply pin of the processor. The input current must be pushing VDD up through the protection diodes.

Is this a low-power design where the current required from the power supply for the PIC and other circuitry is only a few milliamps? If it is, then attempting to clamp inputs to the positive supply rail is not going to work. Methods that either limit the current into the inputs to much lower levels or that clamp the signals to circuit common ("ground") are going to be necessary.

For the 244: yes, 20 mA is the spec'd abs. max for the diodes; see Table 4 line 2 in the datasheet. AC series CMOS logic I believe is rated for 40 mA into the protection didoes, which is the maximum value I can recall as a spec for any IC for the clamping diodes.

I may have mentioned this before: When using clamping diodes of any sort (internal to IC or external) you must also check the current that is possible if the power to the IC is off.

This is the ap note I mentioned previously
https://www.nxp.com/docs/en/application-note/AN4731.pdf

 

Note the warning that appears at the bottom of nearly all devices' Absolute Maximum Ratings section:


A word of advice: THEY MEAN IT.

 

thanks guys, appreciate it. The design is not 'low power' but powered from a series of 12V SLA cells. I am surprised some of the pins are protected (somewhat) by zeners going to the pic (below) and more are not, as well as having dubious voltage dividers with little headroom.

 

This is what I got -

6.06V @ 600uA on 3 x ADC analog inputs
8.50V @ 3.2mA on 3 x GPIO digial inputs
8.50V @ 3.2mA on 1 x 74HCT244 Digital input

So the consensus is that the voltage is too high - for GPIO maximum VCC +/- 0.3V (data sheet says 4.2 to 5.5V)
PIC18F6X27/6X22/8X27/8X22 >> Min 4.2 — Max 5.5 V
- applicable to PIC and 244

Inputs clamp @ 20mA (so not an issue here)

Max Voltage on Analog pins = 5.5V +/- 0.3V ? also with 20mA clamp?

 

Hi Guys,

So a quick question on this - if all analog pins of the PIC are simultaneously loaded what would that mean for the curren clamp? its divided amongst all the inputs? say 5 channels are used is the 20mA clamp divided by 5? Just wondering how the PIC in discussion is so rubust as to not get damaged since some of the pins are clearly getting over loaded with too much voltage.

cheers all.

 

There are four primary issues associated with driving current thru parasitic diodes
in CMOS structure -

1) Excess current dropping internal rail voltages causing noise margins to be compromised.

2) Excess current that actually melts Si and Al and bond wire interconnect.

Modern datasheets spec the limits on current, typically local internal busses,
like a specific port buss, as a limit. Then additionally total limit on supply
pin, eg. sum of all GPIO currents.

3) Triggering parasitic SCR, latchup, shorting out supply rails, and blowing open the
internal Vdd bond wire die to pin pad.

Modern datasheets spec the limits on current to prevent triggering.

4) Excess current that injects charge into substrate that then unpredictably migrates
to some area of logic/functionality to upset "normal" circuit design operation.

Modern datasheets have SCR pin trigger current limits stated.

The industry has a bit of a conundrum, that is protecting inputs with external Si diodes. That
makes an assumption that external Si diode Vth < Internal diode Vth which cannot and
should not be assumed. Alternative is to use Schottky diodes.

http://www.ti.com/lit/wp/scaa124/scaa124.pdf

http://www.ti.com/lit/an/scba004d/scba004d.pdf

Regards, Dana.