Get Error: (vsim-3033)as I am trying to do RTL-timing simulation using Modelsim

Thread Starter

Musheer Abdullah

Joined Mar 4, 2021
hello everyone
please , help me
I finished writing my design using verilog, functional simulation by modelsim is working well. then I synthesized my design by using ( Encounter(R) RTL Compiler RC10.1.306 ) to create the netlist and SDF (standard delay format) files successfully . I used TSMC 0.18μm CMOS process timing library.
I am trying to make timing simulation for netlist design by modelsim using same testbench file I used for functional simulation before .
but unfortunately I get many errors as this;
Error: (vsim-3033) <project file path>(278690): Instantiation of 'BUFTD1BWP7T' failed. The design unit was not found.
this error because this cells 'BUFTD1BWP7T' in the netlist file which has been added from the technology library and it is defined in the library file.
how I can include the timing library in my project in modelsim to overcome this error .
please help me to solve this problem , I don't have enough time ! it is my graduation project and I must finish the timing simulation . thanks in advance

photo for the instantiated cells in my Netlist file
and this photo for the cells definition in the timing library