here it ishi mo,
Do you have a LTSpice asc file to post, showing your best effort, we can then help.
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Actually that is what i am struggling to do. any suggestions pleaseThe first thing is to model the pulse mathematically. It looks like it might be essentially two exponentials, but you probably need to do something to a smooth transition at the peak.
Thank You for sharing.hi mo,
This is the method, shown a close result, up to you now to finalise.
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yes that is exactly my design. now how i can add that transient at load side could you please explain that?hi mo,
I have partially redrawn the circuit with last hierarchical file, but the .lib is missing.
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Its working for me and everything what i want with regards to input filtering is there. I just want to add a load transient pulse at Vbus+ and Vbus-. If u could pls only guide me about that how can i add it. here is my simulation. green is input dc bus voltagr and blue is voltage at switching nodehi mo,
Your LTSpice asc does not work, I have to make some changes
I would like to see your best effort in solving this problem, do you have a copy of the complete original assignment.?
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