Generation of multiple phases out of an incoming clock

Thread Starter

Manish Chowdhary

Joined Jul 29, 2017
5
Hi,

I seek help in understanding a phase generator circuit. This circuit creates 64 phases of the 100MHz input clock each separated by 156.25ps.
Effectively it is creating an output of 6.4GHz from the incoming 100MHz.

I am wondering how the output will look like

1) What would be the output like, will it be a continuous signal with time period of 156.25 ps? (as I have shown in the attachment)
2) What circuit elements are required to generate phases out of an incoming signal?

Thanks in advance,
Manish
 

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Papabravo

Joined Feb 24, 2006
14,253
The normal method of generating higher frequencies from a lower frequency reference signal is to use a phase locked loop. This technique is well known, understood and documented. Once you have the high frequency signal you can divide it down to get precise phase delays. For example you can use two filp-flops to make quadrature clocks with 90° of delay between the edges.
 
Last edited:

ronsimpson

Joined Oct 7, 2019
830
This circuit creates 64 phases of the 100MHz input clock each separated by 156.25ps.
Effectively it is creating an output of 6.4GHz from the incoming 100MHz.
The outputs are all at 100mhz. Each is shifted 156pS.

Phase shift oscillator.
1597238903188.png
I have built the same thing but with many LCs as the delay.

Inside a IC you can have very fast inverters. (150nS delay each) In your case use 64 inverters in a loop. The loop will oscillate. The delay is very related to the supply voltage. I varied the supply voltage of that part of the IC to change the frequency. In your case 100mhz. Now each inverter has 100mhz with a phase shift of 156nS * X. x=1 to 64ghz you are looking for.

edited:
It you XOR and the outputs you will get the
1597239080465.png1597239090286.png
 

andrewmm

Joined Feb 25, 2011
536
Hi,

I seek help in understanding a phase generator circuit. This circuit creates 64 phases of the 100MHz input clock each separated by 156.25ps.
Effectively it is creating an output of 6.4GHz from the incoming 100MHz.

I am wondering how the output will look like

1) What would be the output like, will it be a continuous signal with time period of 156.25 ps? (as I have shown in the attachment)
2) What circuit elements are required to generate phases out of an incoming signal?

Thanks in advance,
Manish
can you draw us a circuit please,
my understanding of what your saying is that you end up with 64, 100 MHz clocks,

is that what you want ?
 

Papabravo

Joined Feb 24, 2006
14,253
I think he wants a 6.4 GHz. clock from a 100 MHz. Reference, and he wants 64 clocks with small phase offsets from each other.
 

Delta prime

Joined Nov 15, 2019
431
hello there :)
my understanding of what your saying is that you end up with 64, 100 MHz clocks
This is out of Blue Sky , only because I do not know your criteria.
T straight forward
The ALTLVDS_RX megafunction provides a limited drop-down list selection for setting the clock and data relationship in non-DPA mode. The parameter is What is the phase alignment of 'rx_in' with respect to 'rx_inclock'. By setting this parameter, the ALTLVDS_RX megafunction calculates the proper capture phase for the serial data.
The phase shift values are based on the rx_inclock period, which can vary depending on your interface. The following are common rx_inclock usage scenarios
I can only think of one example I can possibly steer you in the right direction.
input clock phase shift for capturing data in the ALTLVDS_RX megafunction
The total possible number of capture phase positions depends on the deserialization factor of the interface. For each serial bit period, there are 8 phases available from the fast clock. The fast clock operates at the serial bit rate
if you wish to specify the rising edge of rx_inclock to be center aligned on the third serial bit of the 8 bit word, you would need a total of 20 phase shift increments (8 phase increments for each of the first two bit periods, plus 4 phase increments for the center aligned rising edge in the third bit period).
The fast clock operates at 800 MHz, the same as the data rate. The fast clock period is 1.25 ns, which results in 156.25 ps per phase shift increment. The total required phase shift in this example to describe the input clock and data relationship is 20 * 156.25 ps = 3.125 ns.
Once you calculate the desired phase shift value, enter it in the ALTLVDS_RX variation file
 
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