Generating a short signal on power up for ADC continuous conversion

Thread Starter

128ITSH

Joined Jul 20, 2017
101
Hello everybody.
For the "input" module of an home-brew computer I'm designing now, I will be using an 8 input ADC, the ADC0808.
I have figured out everything required for it except the continuous conversion which I want to use. The data sheet says:
"Continuous conversion may be accomplished by tying the end-of-conversion (EOC) output to the SC input. If used in this mode, an external start conversion pulse should be applied after power up."
How can I generate this short pulse?
Is a pullup resistor enough for this?
adc.png
Or should I use a buffer?
adc2.png
Thanks in advance!
 

crutschow

Joined Mar 14, 2008
25,691
You can use an OR gate, as shown below, to generate a momentary start pulse when the power is applied.
The RC values shown will give about a 3/4 second pulse upon power up.

upload_2017-11-26_19-22-17.png
 
Last edited:

Thread Starter

128ITSH

Joined Jul 20, 2017
101
Or control U1 (replace C1) and use MPU output allowing an easy delay optimisation.

Picbuster
Thank you but in this project I'm not going to use any MCU's, but old 4000 and 7400 logic IC's to create an 8-bit computer.

You can use an OR gate, as shown below, to generate a momentary start pulse when the power is applied.
The RC values shown will give about a 3/4 second pulse upon power up.

View attachment 140247
That looks like a good solution. but I want a faster pulse, so what values do I need to change to make this pulse shorter, and what is the equation for calculating any pulse duration?
 

AnalogKid

Joined Aug 1, 2013
8,708
Pulse width time t is directly proportional to the R-C time constant. For a non-schmitt-trigger CMOS gate:

t = 0.69 x R x C

ak
 

AnalogKid

Joined Aug 1, 2013
8,708
Not sure what you are cautioning against. 0.69 used because it is a 99.5% approximation of the ln of 0.5 (not 2). 0.5 is used because the transition level for non-Schmitt CMOS inputs is nominally 1/2 of Vdd. Given the possible variance in the actual transition level of any particular gate input, I think 99.5% is accurate enough.

ln (0.5) = -0.693147... The minus sign combines with another minus sign in the long-form equation for an R-C voltage curve, yielding the (+)0.69 in the equation above.

ak
 
Not sure what you are cautioning against. 0.69 used because it is a 99.5% approximation of the ln of 0.5 (not 2). 0.5 is used because the transition level for non-Schmitt CMOS inputs is nominally 1/2 of Vdd. Given the possible variance in the actual transition level of any particular gate input, I think 99.5% is accurate enough.

ln (0.5) = -0.693147... The minus sign combines with another minus sign in the long-form equation for an R-C voltage curve, yielding the (+)0.69 in the equation above.

ak

Nonetheless, 0.69 is an approximation to Ln(2) and not Ln(0.5).
 

Thread Starter

128ITSH

Joined Jul 20, 2017
101
That OR gate method is known not to work very well because of the EOC input. A better way is a state machine with a doubly synchronised input which you then connect the or gate to.

aa
What is the reason for that? EOC is an output and not an input. According to the datasheet EOC goes high when the conversion has ended.
 
Top