Gate voltage: schemo mistake or TRUTH?

Thread Starter

Delian Diver 1

Joined Dec 25, 2015
4
Hello!
I'm currently building a clone of vintage analog synth.
I got success with VCOs, LFOs, VCF and some other parts of it. But when time had come to insert SSM2050 (old ADSR chips of Solid State MicroTech), I have checked all the voltages in the socket. I was surprised to measure 16.5V at GATE and TRIGGER pin of SSM2050 just before I put the ICs into the sockets.
The problem is that there small circuit "Gate Processor" that is intended to control the input of gate signal as it can be negative or positive.
Here is the picture of it:
The original one:

_Kobol_Gate_Processor_original.jpg

And redrawn:

_Kobol_Gate_Processor.jpg
After the CI1 TL084 the input GATE of any voltage becomes about 16.4V. Even that the original datasheet of the SSM2050 does not have the maximum voltage for GATE pin I think the 16.4V might kill the ICs. I thought that I have made a mistake and simulated the circuit it LTSpice - no way! 16.4V... GATE with 16.4 V? Is not it too high for GATE signal?

The rest of the circuit:
_Kobol_Gate_2_ADSR.jpg

Also You may see that the 5/8 Port has a description 0/+5V which means GATE voltage has to be 5V maximum.
So what is the your opinion about this?
 
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