How can I fix plateau in this gate signal, my input has dead time but you see at the output there is no dead time , how can I fix it

 

hi karas,
Please post your LTS asc file for the circuit, so that we can run it.
Labels identifying the Nodes would help.
E

 

Will the gate withstand 24V peak?

 

Will the gate withstand 24V peak?

yes

 

The capacitors in series with diodes look problematic to me. How are the caps discharged?

 

Try this circuit:

 

The capacitors in series with diodes look problematic to me. How are the caps discharged?

This Zener to limit the voltage on the gate , and the capacitor discharge through the schottky diode

 

Try this circuit:
View attachment 145419View attachment 145420

I did try it , and is not working(try to do it at high frequency), I think at the dead time we have to reset the transformer and I am trying to figure how to do this

 

 

View attachment 145438

Thanks, can you do it please with 2 secondaries, the rail voltage is about 750Vdc so i need high isolation between the 2 gates

 

hi karas,
Please post your LTS asc file for the circuit, so that we can run it.
Labels identifying the Nodes would help.
E

 

View attachment 145438

Danko, may I ask what program you are using to make the simulation, please?

 

Thanks, can you do it please with 2 secondaries, the rail voltage is about 750Vdc so i need high isolation between the 2 gates

Yes, it is:

In reality, you should to force transistor to close, by negative voltage on gate:

Maybe very well working circuits below will useful for you:
Source: http://www.kalyaev.com/2010/20101129/Invertor-01.php.htm

 

Danko, may I ask what program you are using to make the simulation, please?

NI Multisim.

 

NI Multisim.

Thank you for that, will need to look into it.

 

Research the www.danyk.cz/svar_en.html page how effectively produce the gate discharging by circuit very similar to Your`s. Take off the part after slash and find a wide spectra of materials explaining what and why. The mosfets and igbt`s are just like a fragile wife who dont give before feel comfortable. And bad gate de-lading means feel very uncomfy.

 

Yes, it is:
View attachment 145488
In reality, you should to force transistor to close, by negative voltage on gate:
View attachment 145493
Maybe very well working circuits below will useful for you:
Source: http://www.kalyaev.com/2010/20101129/Invertor-01.php.htm
View attachment 145505 View attachment 145506

Thanks, how much you dissipate in the gate resistor , i think about 10W? is this right?

 

Research the www.danyk.cz/svar_en.html page how effectively produce the gate discharging by circuit very similar to Your`s. Take off the part after slash and find a wide spectra of materials explaining what and why. The mosfets and igbt`s are just like a fragile wife who dont give before feel comfortable. And bad gate de-lading means feel very uncomfy.

Thanks , it works

 

Thanks, how much you dissipate in the gate resistor , i think about 10W? is this right?

Yes, 10W, if you like to use Zeners, but only 1...2W without Zeners View attachment 145505 View attachment 145506
Edit: And it depends on voltage of secondary winds. If Zener voltage will a bit higher than secondary wind voltage, then no excessive power.

 

In attachment - simulated 50kHz inverter, 1500V peak-peak, 4A current in load 185Ohm.
Two circuits, one - simple, based on View attachment 145506
Works good.
Second - based on www.danyk.cz/svar_en.html
Up to 21A current throughout transistors Q1, Q2 at a time.