GATE DRIVE SIGNAL (plateau problem)

Discussion in 'General Electronics Chat' started by karas, Feb 6, 2018.

  1. karas

    Thread Starter Active Member

    Sep 8, 2011
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    How can I fix plateau in this gate signal, my input has dead time but you see at the output there is no dead time , how can I fix it

    upload_2018-2-6_21-30-49.png
     
  2. ericgibbs

    Moderator

    Jan 29, 2010
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    hi karas,
    Please post your LTS asc file for the circuit, so that we can run it.
    Labels identifying the Nodes would help.
    E
     
  3. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    Will the gate withstand 24V peak?
     
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  4. karas

    Thread Starter Active Member

    Sep 8, 2011
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    yes
     
  5. RichardO

    Senior Member

    May 4, 2013
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    The capacitors in series with diodes look problematic to me. How are the caps discharged?
     
  6. Danko

    Member

    Nov 22, 2017
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    Try this circuit:
    problem_1.png problem_2.png
     
  7. karas

    Thread Starter Active Member

    Sep 8, 2011
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    This Zener to limit the voltage on the gate , and the capacitor discharge through the schottky diode
     
  8. karas

    Thread Starter Active Member

    Sep 8, 2011
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    I did try it , and is not working(try to do it at high frequency), I think at the dead time we have to reset the transformer and I am trying to figure how to do this
    upload_2018-2-7_20-14-25.png
     
    Last edited: Feb 7, 2018
  9. Danko

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    Nov 22, 2017
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  10. karas

    Thread Starter Active Member

    Sep 8, 2011
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    Thanks, can you do it please with 2 secondaries, the rail voltage is about 750Vdc so i need high isolation between the 2 gates
     
  11. karas

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    Sep 8, 2011
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  12. shortbus

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    Sep 30, 2009
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    Danko, may I ask what program you are using to make the simulation, please?
     
  13. Danko

    Member

    Nov 22, 2017
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    Yes, it is:
    Gate_driver_2.png
    In reality, you should to force transistor to close, by negative voltage on gate:
    Gate_driver_3.png
    Maybe very well working circuits below will useful for you:
    Source: http://www.kalyaev.com/2010/20101129/Invertor-01.php.htm
    driver_module.png fet_module.png
     
    Last edited: Feb 9, 2018
  14. Danko

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    Nov 22, 2017
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    NI Multisim.
     
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  15. shortbus

    AAC Fanatic!

    Sep 30, 2009
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    Thank you for that, will need to look into it.
     
  16. Janis59

    Active Member

    Aug 21, 2017
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    Research the www.danyk.cz/svar_en.html page how effectively produce the gate discharging by circuit very similar to Your`s. Take off the part after slash and find a wide spectra of materials explaining what and why. The mosfets and igbt`s are just like a fragile wife who dont give before feel comfortable. And bad gate de-lading means feel very uncomfy.
     
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  17. karas

    Thread Starter Active Member

    Sep 8, 2011
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  18. karas

    Thread Starter Active Member

    Sep 8, 2011
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    Thanks , it works
     
  19. Danko

    Member

    Nov 22, 2017
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    Yes, 10W, if you like to use Zeners, but only 1...2W without Zeners View attachment 145505 View attachment 145506
    Edit: And it depends on voltage of secondary winds. If Zener voltage will a bit higher than secondary wind voltage, then no excessive power.
     
    Last edited: Feb 12, 2018
  20. Danko

    Member

    Nov 22, 2017
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    In attachment - simulated 50kHz inverter, 1500V peak-peak, 4A current in load 185Ohm.
    Two circuits, one - simple, based on View attachment 145506
    Works good.
    Second - based on www.danyk.cz/svar_en.html
    Up to 21A current throughout transistors Q1, Q2 at a time.
    Gate_driver_simple.png Gate_driver_Danik.png
     
    Last edited: Feb 14, 2018
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