Are there any gate current of the nmos Mn2(attached image) when it is used as a switch? Nmos Mn2 acts as a switch to charge and discharge the capacitor.

How can I calculate the gate current through the mosfet?
How does the gate current affect the charging/discharging of the capacitor?

 

The gate of a MOSFET is insulated from the drain-source channel. The gate leakage current is no greater than 100nA. For switching applications, you have to consider the gate capacitance and the frequency of the switching signal. This has very little to do with the capacitor connected on the load side.

 

The gate of a MOSFET is insulated from the drain-source channel. The gate leakage current is no greater than 100nA. For switching applications, you have to consider the gate capacitance and the frequency of the switching signal. This has very little to do with the capacitor connected on the load side.

Ahm, why does when I connect another circuit (SR latch or XOR gate) in parallel with the MN2 gate the clock signal distorts?

 

Clock signal is produced by the same circuit, not an external clock.

 

Ahm, why does when I connect another circuit (SR latch or XOR gate) in parallel with the MN2 gate the clock signal distorts?

Does the circuit contain enough "decoupling" capacitors?

 

Does the circuit contain enough "decoupling" capacitors?

Ah okay, thanks I get it. Decoupling capacitors will cause distortion in the signal.

 

Ah okay, thanks I get it. Decoupling capacitors will cause distortion in the signal.

If I understand you correctly then you are not right.

Better power supply will reduce power supply impedance. This will reduce distortions caused by fluctuations in the power supply.

I think what you may be seeing is the Miller effect. This is caused by gain in the FET and its drain to gate capacitance. It is this larger than expected capacitance that is loading your clock signal.

 

Ah okay, thanks I get it. Decoupling capacitors will cause distortion in the signal.

No, decoupling caps prevent/lessen distortion. They provide a 'buffer' when the devise is switching. To get better answers to your problem you need to show more of your schematic. Showing one mosfet isn't giving enough to work with.

 

Gate drive current, MOSFET switching, Miller plateau...

https://www.google.com/url?sa=t&rct.../slua618.pdf&usg=AOvVaw2iuo-DEdY01npKFn-UdmVA


Regards, Dana.

 

I assume you are once again talking about very small geometry FETs on an integrated circuit.

If you are simulating the circuit, why not just measure the current? If you convert the FET model from a three-terminal device to the full equivalent circuit you should be able to see not just the gate current but where that current is going. There may be a way to do this quite easily, but I'm no simulation expert.