Hi guys,

Today I was playing with LTspice and started testing with some transistors. I created two identical circuits with two very similar transistors namely the BFR183 and BFR193. I need some confirmation on reliability. I have seen these BJTs have incredible gain. With an input voltage of +/- 100uV I can get +/- 10mV or even 12mV. Since I'm still studying these simulators, I ask for confirmation if it is really possible to obtain such a high gain with this simple scheme and transistor. I am also attaching the datasheet links but it seems to me that the gain is too high when compared to the indicated parameters. The two transistors should be part of the standard LTspice library so you don't need an external file but I'm not sure because I use the extended libraries. So I also attach the .model text in case it helps. Thank you!





BFR183


BFR193


ASC File


.MODEL BFR183 NPN(IS=1.0345f ISE=1.6818E-14 ISC=1.3559f XTI=3 BF=115.98 NR=0.99543 IKF=0.14562 IKR=0.013483 XTB=1.5 VAF=14.772 VAR=3.4276 VJE=1.0792 VJC=1.1967 RE=1.3435 RC=0.20486 RB=2.5426 RBM=1.0112 IRB=0.00043801 CJE=2.3077E-14 CJC=4.6011E-13 XCJC=0.053823 FC=0.54852 NF=0.80799 BR=10.016 NE=1.2149 NC=0.85331 MJE=0.45354 MJC=0.3 TF=2.2746E-11 TR=1.0553n ITF=0.0018773 VTF=0.50905 XTF=0.36823 EG=1.11 VCEO=20 ICRATING=65m MFG=SIEMENS)

.MODEL BFR193 NPN(IS=2.738E-16 ISE=1.0627E-14 ISC=3.7409E-17 XTI=3 BF=125 BR=14.267 IKF=0.26949 IKR=0.037925 XTB=1.5 VAF=24 VAR=3.8742 VJE=0.70276 VJC=1.1828 RE=0.76534 RC=0.11938 RB=1.8368 RBM=1 IRB=0.00091763 CJE=1.1824f CJC=9.3503E-13 XCJC=0.053563 FC=0.72063 NF=0.95341 NR=1.4289 NE=1.935 NC=0.94371 MJE=0.48654 MJC=0.30002 TF=1.8828E-11 TR=1.0037n ITF=0.00096893 VTF=0.8 XTF=0.69477 EG=1.11 VCEO=20 ICRATING=80m MFG=SIEMENS)

 

Why dont you try to verify the gain by calculation?
The gain is app. G=-gm*Rc with transconductance gm=Ic/Vt (Ic: DC quiescent current and Vt=26mV)

 

Why dont you try to verify the gain by calculation?
The gain is app. G=-gm*Rc with transconductance gm=Ic/Vt (Ic: DC quiescent current and Vt=26mV)

Sorry guy I'm not familiar with these calculations yet!

 

The gain is about 100 times in the simulation that has no stray capacitance to ground at the output.
The gain of a real circuit at the very high frequency will be less.

 

Sorry guy I'm not familiar with these calculations yet!

But I gave you the formula - thats all you need.

 

I ask for confirmation if it is really possible to obtain such a high gain with this simple scheme and transistor. I am also attaching the datasheet links but it seems to me that the gain is too high when compared to the indicated parameters.

What are these "indicated parameters" that you are referring to and what comparisons are you making to conclude that the gain is too high?

Are you sure that those are the exact circuits you are simulating?

Assuming negligible base current, the base voltage established by the bias network would be

Vb = 12 V * [2.7 kΩ / (22 kΩ + 2.7 kΩ)] ~= 1.3 V

This would place the emitter voltage at about

Ve = Vb - 0.7 V = 0.6 V

This would yield an emitter current of around

Ie = Ve / 10 Ω = 60 mA ~= Ic

Which would result in a drop across the collector resistor of

V_R10 = Ic * 330 Ω ~= 20 V

This indicates that the transistor should be in hard saturation (under the assumption of negligible base current).

The other possibility is that your base current is representing a considerable load on your bias network and considerably dropping the base voltage.

The current in the top base bias resistor is limited to no more than 12 V / 22 kΩ, or 545 µA.

The collector current is limited to no more than 12 V / 330 Ω, or ~36 mA

If the beta is 100, then that would require about 360 µA of base current. even if the collector current is only half the limit, that's still a significant fraction of the bias network current, so your transistor is loading your bias network pretty heavily.

 

DaniKowa
I wanted to tweak your circuit: take into account the internal resistance of the signal source and use more complete transistor models. I have models that take into account the parasitic parameters of the transistor body. But I couldn't download the schematic file, and I am too lazy to draw the scheme myself - you uploaded the file to a file-sharing site, which I am not a member of. Also you have to carefully consider the load. To use the same cascade as the load as an example. And then you will not be surprised by the result.

 

Thank's for the kind replies,

I found this calculator on https://www.guitarscience.net/calcs/ce.htm . I entered all the data that I found with the spice simulation and the result is a gain of 48.08dB which is obviously excessive compared to what is described on the datasheet which should be 17db recommended (is that right?) so to get within this parameter :

I changed the RE from 10 to 47ohm
Eliminated the bypass cap parallel to RE
Changed R8 to 4,7k
Changed R7 to 560



I hope now it's ok. Input */-100u and Output +/- 600uV for both transistors which is much lower than before also because the bypass cap has been removed.

The next question is: If the circuit is now ok, is it possible to reinsert the bypass capacitor without losing stability or is it recommended not to use it anyway?

@Bordodynov try now to download if you want. It may be ok.

 

hi,
When posting regarding a LTSpice circuit problem, please post the asc file.
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hi,
When posting regarding a LTSpice circuit problem, please post the asc file.
E

The link I put in the first tread leads to the download to an asc file. Unfortunately I see (at least for me) that the post is badly paginated but I don't know why. I tried the link and now it works. Tell me it works for you too. I didn't put the asc file of the second modified circuit to get confused. Do you want me to upload the modified asc file as well?

 

hi,
The original asc link did not work, it does now.
Post the modified asc file.
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hi,
The original asc link did not work, it does now.
Post the modified asc file.
E

Here the file modified.

 

hi Dani,
Downloaded and ready, is there any specific point in the circuit you want me to check.
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Hi,
This is what I see, changed the V3 source model.

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hi,
This what I see using your source model and settings.??
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I corrected the resistor from 4k7 because it was badly written. Despite this I had different results from yours, then I understood why. I had to delete all the files created with the previous simulations leaving only the asc file and now they are the same as yours.

Question: If I add the bypass cap on the RE (10uF should be enough) obviously I increase the gain but do I lose stability again? It would bring a gain increase from 16 to 40db.

 

hi D,
This is with 10uF in parallel with RE,.
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@DaniKowa
BTW: Use AC=1 for AC analysis, it gives an actual db plot.

 

Thank you Eric!

 

One last question if possible @ericgibbs . I seen that the phase plot becomes linear at around 500Khz. Before 500Khz it is not. For which is it non-linear before 500Khz?

 

hi D,
This partly due to input and output capacitor impedances,
This steps both the value, a bit messy to read, but you get the idea.
E