Hello, I am making a 32bit coincindent decoder for a memory array, which requires a fanout-of-4 and fanout-of-8 nand gate. How do I calculate the size of pmos and nmos transistors for these fanouts? I do not plan to optimize for delay, only low power consumption.

 

The simple approach will be to use low current CMOS logic, where fan-out is normally not an issue.

 

The simple approach will be to use low current CMOS logic, where fan-out is normally not an issue.

He's asking about sizing the NMOS and PMOS transistors on an IC design.

 

I am making a 32bit coincindent decoder for a memory array, which requires a fanout-of-4 and fanout-of-8 nand gate. How do I calculate the size of pmos and nmos transistors for these fanouts?

It's partially dependent on the process.

 

Hello, I am making a 32bit coincindent decoder for a memory array, which requires a fanout-of-4 and fanout-of-8 nand gate. How do I calculate the size of pmos and nmos transistors for these fanouts? I do not plan to optimize for delay, only low power consumption.

If you are trying to optimize for low power, then you need to do so within a delay constraint, otherwise you can make it super, super slow so that it draws almost no power.

Since you are asking this in the IC Design forum, presumably you are implementing this logic on the same IC as the memory. Is that correct? If not, what is between the logic you are designing and the memory array, including such things as pads, ESD protection, package parasitics, PCB trace characteristics?

In general, characterize your worst-case load, which will be mostly capacitive in most cases. Then determine the slowest speed and worst delay that is tolerable. These are not quite the same thing, as you might be able to tolerate a long delay, but need a pretty fast switching speed once switching begins in order to avoid excessive shoot-through. Once you have that determined, run corner simulations over the temperature range and adjust your transistor sizes so that they just meet spec with whatever margin you determine is desirable. To little margin, and the design might not work properly at all conditions, to much margin and you are consuming more power than you need.

But before you go through all that, ask yourself just how critical it is that you optimize the design for power. Unless there are a LOT of these on the chip, and/or they are running at a high frequency (unlikely, given that you say you don't care about delay), then how much power are you really going to save by optimizing these two NAND gates?

Instead, simulate minimum geometry NAND gates and see if they are fast enough and then estimate the total power consumed by them in the design and determine if that is tolerable. If it is, you are done and can move on.