We don't either, as you haven't posted your best attempt so far.I don't know why
You beat me. The best I could do is six 2-input NAND gates.I have the answer which uses 5 NANDs but my professor says this circuit only needs 4 (he is skipping on the A' NAND and I don't know why)
First, you need to show your best attempt to solve your homework problem. We can then look for errors and provide hints and suggestions -- we can't just give you the answer.I have the answer which uses 5 NANDs but my professor says this circuit only needs 4 (he is skipping on the A' NAND and I don't know why)
The circuit in post #8 - if you read what I wrote, is the original logic statement, implemented as given, to show what the required output actually is. I haven't shown the actual 4 NAND result, but hinted as to how to get to it as I didn't want to give it away - yet!Unfortunately neither the post #8 circuit nor the post #9 circuit meets the thread title requirements.
Have you actually tested the truth table for your 5 gate solution? Does it actually give the required output?I have the answer which uses 5 NANDs but my professor says this circuit only needs 4 (he is skipping on the A' NAND and I don't know why)
Were you able to solve the circuit with a maximum of four 2-input NAND gates? It appears TS has left the building so I'd appreciate the answer. I spent quite a while trying to solve it.The circuit in post #8 - if you read what I wrote, is the original logic statement, implemented as given, to show what the required output actually is. I haven't shown the actual 4 NAND result, but hinted as to how to get to it as I didn't want to give it away - yet!
That's what happens if you try to use DeMorgan on the /BC + /BD clause first, like this, /BC + /BD = /B(C + D ) = /B/(/C/D) Call that X and do /A + X = /(A/X) = /(A/(/B/(/C/D))) which requires 5 NAND gates, three to give /B, /C, /D, one for /(/C/D),Were you able to solve the circuit with a maximum of four 2-input NAND gates? It appears TS has left the building so I'd appreciate the answer. I spent quite a while trying to solve it.
The constraint isn't 2-input NAND gates, just NAND gates, as evidenced by the TS's solution attempt, which included a 3-input gate.Were you able to solve the circuit with a maximum of four 2-input NAND gates? It appears TS has left the building so I'd appreciate the answer. I spent quite a while trying to solve it.
As soon as you allow the use of NAND gates with more than two inputs, the solution drops out immediately by applying DeMorgan's to the original expression. This is why I asked, in my original response, whether the solution allowed the use of n-input gates.That's what happens if you try to use DeMorgan on the /BC + /BD clause first, like this, /BC + /BD = /B(C + D ) = /B/(/C/D) Call that X and do /A + X = /(A/X) = /(A/(/B/(/C/D))) which requires 5 NAND gates, three to give /B, /C, /D, one for /(/C/D),
another for /(/B/(/C/D)) and the fifth for bringing in the A. I couldn't see how to simplify that to the 4 gate solution, though clearly it must be possible...
The 4 gate solution is this:
View attachment 317640
Exactly, and if you construct the original logic with gates, as I did in post #8 its obvious by inspection - convert the ANDs to NANDs. remove the invert on A and replace the OR with a NAND...As soon as you allow the use of NAND gates with more than two inputs, the solution drops out immediately by applying DeMorgan's to the original expression
by Aaron Carman
by Aaron Carman
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