floyd12-25, op-amp input offset voltage

steveb

Joined Jul 3, 2008
2,436
I agree with Ron H, in that you do need to study this on your own using on line references and books. I'll look around to make some recommendations later.

Your questions could generate very detailed answers and you may very well get different opinions from different people. I don't think I can do justice to the answers you need, in full detail, but I can try to make a passing comment about each of your questions.

Q1 Your confusion about common mode and differential mode is likely the result of not approaching the subject in a proper and detailed way. The course and the book are what they are, and you are limited by them. I've always believed that sometimes a simplified approach is harder than a full and proper headlong dive into the details. Ron's comments about tracking down good references and learning is right on here.

Q2 Don't worry about how to do it practically because you won't need to. If by some odd chance you ever need to, it will happen long after you know the answer to your question.

Q3 Yes, the current is consumed in the sense that there is a voltage and current that determines power, which is consumed. It's a small power that you don't need to ever worry about. I guess it is called bias current because it is needed to drive or bias the input stage transistors. Without a DC path on the inputs, the OPAMP won't operate properly.

Q4 This gets back to common mode and differential mode issues. You need to learn how common mode and differential mode signals are defined, and how the OPAMP behaves to these two types of signals. Note that any input signal can be represented as a sum of a differential mode signal plus a common mode signal.

Q5 Don't worry about measuring this. It's a circuit model. The values are determined such that they best agree with measurements. Knowledge of the actual circuit design and creative measurements can be used to get a good model, but this is far beyond the level you are at.

Q6 The voltage offset from the input current is only one contribution to the total offset voltage.

Q7 Rise time and bandwidth are always related and are basically indications of the same information in both the time domain and frequency domain. The relation between the two is determined by Fourier analysis and linear system theory. In a nutshell, high bandwidth gives fast rise time for a step input. Low bandwidth gives slow rise time for a step input.

Note that a step is defined to be something that starts at zero and switches instantly to another value at time zero, and then stays there for all time afterwards. A pulse is not a step because a pulse eventually goes back down to zero.

Q8 Yes
 

Ron H

Joined Apr 14, 2005
7,063
I worked on the first 6 questions, but you may find that the answers just bring up more questions.
**************************************

Q1:When an op amp has negative feedback around it, and the output is not saturated, then, due the extremely high open loop gain, the inverting (-) input voltage will be virtually equal to the voltage on the noninverting (+) input pin. For example, if the +input is +10V, then the inverting input will also be at +10V (minus a few microvolts).

Q2: Some op amps have offset trim pins, in which case you follow instructions in the datasheet. If offset adjust pins are not provided, you can sum a small voltage into the +input, or a small current into the -input.

Q3:The input bias currents have to flow through whatever components you have connected to the input pins. There is no magic. It is a current, just like the current in any other part of the circuit. You have to account for it when you design a circuit around an op amp.
For more info on why it is called "bias" current, see Biasing.http://en.wikipedia.org/wiki/Biasing

Q4 and Q5: You don't need to have access to the "ground" inside the op amp. In fact, most op amps don't have an internal ground. All you need to do is apply an AC voltage (or varying DC voltage) on the input or output, and note the AC current. Use Ohm's law to calculate the resistance. In the case of the output, apply the voltage in series with a resistor (and a capacitor), then consider that the output resistance is part of a voltage divider. Note that the op amp should have feedback applied, and biased (there's that word again) so that the output is not saturated. Also check to see that your measurement hardware (long wires, stray capacitance) do not cause the op amp to oscillate, as this will give you erroneous results.

Q6: The input bias current flows through the resistors on the input pins. If the resistance on the +pin is equal to the resistance on the -pin, and the bias currents are equal (zero offset current), then the result is simply a shift in common mode voltage by the amount Rin*Ibias. If the resistors are equal, but the bias currents aren't, (non-zero offset current), then an offset voltage is generated equal to Rin*Ioffset.

EDIT: Steve, I guess we posted at almost the same time.
 

Thread Starter

PG1995

Joined Apr 15, 2011
832
I genuinely thank you, Steve, Ron, for your help.

I still do have a lot of confusions but I understand that's the best you can do to help me in view of my limited knowledge of the subject. By the way, I'm sure they won't be asking questions about this stuff in the exam. I was rather making those queries for my own knowledge. And I'm sorry about the attachment picture. I see it now that after uploading the resolution of the image decreases and it would have been hard for you to read the stuff. Once again, I offer my thanks.

Best wishes
PG
 

steveb

Joined Jul 3, 2008
2,436
Question 1: Yes, and yes.

Question 2: It is the "input" resistor.

Question 3: The author's statement is correct because the use of feedback is the definition of closed loop. Hence the resulting gain is a reduced closed loop gain, but it is reduced in comparison to the open loop gain. Open loop gain can not be reduced, unless the opamp design itself is modified.

Stable voltage gain can mean two independent things. First, there is the usual idea of closed loop AC stability, without which the amplifier would become an oscillator. Then, there is the idea of being DC stable with respect to external disturbances, such as temperature changes. If the opamp characteristics are sensitive to external disturbances, the closed loop gain will not be very sensitive due to the benefits of feedback. Traditionally, the latter issue is talked about with the terminology of "sensitivity" or "robustness" of the design, but sometimes "stability" is used informally. Since the author is making a passing statement. I would assume that both meanings are implied.
 
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t_n_k

Joined Mar 6, 2009
5,455
I'll look at Q1-3.

Q1: If you tie both differential inputs to the same voltage (e.g ground) then you would expect the output to be zero. In practice any output in the absence of an input differential would be considered as an output offset.

Q2: For the purpose of the exercise, consider A2 input (2) as connected to ground or zero volts. If A2 were ideal then with A2 feedback as shown, the A2 + & - inputs would be at the same potential, i.e. ground or zero volts. Now analyzing A1 gain under those conditions you might be able to see the lower terminal of RG is also effectively at ground potential. This would then lead you to surmise the A1 gain is as shown.

Q3: For the purpose of this exercise now consider A1 input as grounded. With Vin2 the voltage at A2 output would be (1+R2/RG)*Vin2. This would induce a current in R1, R2 and RG of i=[(1+R2/RG)*Vin2]/(R2+RG). The output at A1 due to this current would be -i*R1. From this you deduce that the gain magnitude from Vin2 input to A1 output would be -i*R1/Vin2. You could do the rest from here.
 

t_n_k

Joined Mar 6, 2009
5,455
For Q4:

Yes it's a small but valid point which, as it happens, has no bearing on the correctly developed overall analysis. Probably an oversight and technically incorrect - although not without some allowable "justification". The author might have better referred to the difference amplifier (comprising A3 and R3 to R6) inputs rather than simply op amp A3 inputs.

For Q5:

If R3=R4=R5=R6 then the output of the A3 amplifier stage would simply be Vout2-Vout1 as stated in the text. You should prove this for yourself by doing the analysis of the A3 stage from first principles.

For Q6:

As suggested by others try doing some extra research work yourself - Google "instrumentation amplifier with binary gain control"
 

Thread Starter

PG1995

Joined Apr 15, 2011
832
Thanks a lot, t_n_k. It was really nice of you to help me with all the given queries.

I have read your replied several times and I'm still struggling with the stuff. I think I need to go through all this in steps. So, let's start with your reply to Q2.

t_n_k said:
Q2: For the purpose of the exercise, consider A2 input (2) as connected to ground or zero volts. If A2 were ideal then with A2 feedback as shown, the A2 + & - inputs would be at the same potential, i.e. ground or zero volts. Now analyzing A1 gain under those conditions you might be able to see the lower terminal of RG is also effectively at ground potential. This would then lead you to surmise the A1 gain is as shown.
Why should I consider the input (2) of A2 to be connected to a virtual ground when it's not? What's the basis for this 'huge' assumption? I have an understanding of a virtual ground from the derivation of the expression for gain of an inverting amplifier. As you yourself say that if the inverting input (2) of the A2 is at ground level then it's non-inverting input (3) would also be at the same level. That's correct because op-amp always drives to make it differential voltage zero. But in the first place I don't see how input (2) is at ground level and secondly even if it is then there is a contradiction because non-inverting input of A2 is being supplied with V_in2+V_cm which means the non-inverting input is not at zero level. I hope I have stated my confusion clearly. Now please help me with it. Thank you.

Regards
PG
 

t_n_k

Joined Mar 6, 2009
5,455
Hi PG1995,

I'm employing a deductive line of reasoning. I can assume whatever I like about the inputs that are applied to the A1 and A2 terminals. I only need to ensure I set both inputs to a valid potential - i.e. one within the common mode range. If I choose to set one of the inputs to zero volts that is perfectly reasonable. The value of doing so allows me to deduce the effect [at either of the A1 or A2 amplifier outputs] of having one input set to zero volts and the other set to a non-zero value. I still have a difference input to the overall instrumentation amplifier. The underlying justification for doing so is that the entire circuit is assumed to be linear in its operation - if it's not, then none of the preceding or ongoing analysis will be valid.

Assuming circuit linearity is valid, I can apply zero volts input to the A2 side and note what happens at the A1 output with a non-zero A1 input applied. I can then switch conditions by making A1 input zero volts and A2 input a non-zero value and again note what occurs at the A1 output. The linear summation of the two responses in terms of the effective gain to the A1 output from either A1 or A2 input gives me the complete picture when both inputs are at a non-zero value.

The symmetry of the circuit also allows me to make similar conclusions for the effective gain relationship from A1 & A2 inputs to the A2 stage output.

If my approach is untenable for you then I doubt I can be of any further assistance. In that case I'll pass the baton on to another forum member. :)
 

Thread Starter

PG1995

Joined Apr 15, 2011
832
Hi t_n_k

I think we can solve it now. I was just going to edit my last post just to ask you to hold back your reply and energy but I see you have already replied! I have found a good reference and will post the images in some time. I'm sure that would make it easier for you to explain it to me how the circuit works. So, you don't need to pass the baton to anyone else unless someone forcibly take it away from you! :)

Regards
PG
 

Thread Starter

PG1995

Joined Apr 15, 2011
832
Hi :)

I think the book I'm using is quite confusing and shallow sometimes. The instrumentation circuit circuit uses difference amplifier in the second stage (I think the author should have mentioned difference amplifier briefly for the sake of this important instrumentation amplifier even if he didn't want to cover thoroughly). Most of my queries can be answered using the attached reference. The material is quite self-explanatory. Please follow the external link for high-quality image. Thank you.

Link: http://img848.imageshack.us/img848/4194/malvinoinstrumentation7.jpg

Regards
PG
 

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t_n_k

Joined Mar 6, 2009
5,455
Hi

Could you please help me with the queries included in the attachment? Thank you. For high resolution copy of the attachment, please follow the link: http://img521.imageshack.us/img521/4544/floydcomparatorapplicat.jpg

Regards
PG
Q1: Correct

Q2: The diode protects the transistor from the back emf of the relay coil generated when the relay is switched off by the transistor switching off.

Q3: You are correct - the comparator +ve terminal voltage needs to be slightly higher than the negative terminal voltage for the comparator output to change state. Generally we are only talking of a couple of miilivolts (or less) difference because the comparator has a very high open loop gain.
 

Thread Starter

PG1995

Joined Apr 15, 2011
832
Thank you, t_n_k.

In case you didn't see it there are also two queries at the bottom.

And could you please elaborate a little on the role of diode in Q2. I understand that relay is an inductor which will keep on pushing the current for some time even when the transistor is switched. What does back emf mean in this case?

Thanks a lot for the help.

Regards
PG
 

t_n_k

Joined Mar 6, 2009
5,455
This is where you need to do some of your own investigation / research. Otherwise we forum members who respond to questions end up becoming unpaid tutors - which is not our role.

Google "back emf clamping diode"

Regarding op-amps and comparators. While there are similarities in some internal design aspects of the two devices they are really quite different "animals" in the electronic zoo. Again this is something you can quite readily investigate yourself.
 

Thread Starter

PG1995

Joined Apr 15, 2011
832
This is where you need to do some of your own investigation / research. Otherwise we forum members who respond to questions end up becoming unpaid tutors - which is not our role.

Google "back emf clamping diode"

Regarding op-amps and comparators. While there are similarities in some internal design aspects of the two devices they are really quite different "animals" in the electronic zoo. Again this is something you can quite readily investigate yourself.
Hi t_n_k

I'm sorry if you felt this way. As you can easily guess I'm an English learner and also new to this technical sphere so many a time I don't know the proper search phrase to use (and sometimes googling make things more complex for me). I was able to understand it after using your suggested phrase, "back emf clamping diode with replay".

As far as comparators and op-amps are concerned. I did google comparator and became more confused because it exposed me to more details than I wanted to know. I just wanted very basic information. Anyway, thank you for the help and almost all of my queries have been answered.

Regards
PG
 

t_n_k

Joined Mar 6, 2009
5,455
Q1. Yes, it's a decision based on a purely practical approach. For instance, most electronics hobbyists these days would at least have ready access to ±1% resistor values. In reality one must also consider the capacitor value & available tolerances as well. The result of choosing the nearest standard (rather than "exact") values for components is probably not going to effect the outcome unduly unless one has very stringent design requirements.

Q2. For a single pole case there is only one respsonse type available. Damping factor has no real meaning in this instance since it is normally specified in relation to higher order functions.

Q3. Cascading simple single pole stages won't give you a Butterworth response as no means exists for the formation of complex roots.
 

Thread Starter

PG1995

Joined Apr 15, 2011
832
Thanks a lot, t_n_k.

Please help me with the queries below so that I can understand the topic fully. Thank you.

1:

Q2. For a single pole case there is only one respsonse type available. Damping factor has no real meaning in this instance since it is normally specified in relation to higher order functions.
And what response it it? Is it Chebyshev, Butterworth or Bessel?

2:
Q3. Cascading simple single pole stages won't give you a Butterworth response as no means exists for the formation of complex roots.
In the attachment, both circuits are 3rd order filters. In 'Diagram 1' we have a 3rd order low pass filter. Assume that the cascaded filters in 'Diagram 2' also constitute a multi-stage low pass filter. According to you, only the 3rd order filter in 'Diagram 1' would give us Butterworth response. Does the 3rd order filter in 'Diagram 2' offer any advantage over the filter in 'Diagram 1'? In other words, under what requirements the filter of 'Diagram 2' would be more apt choice to use?

3:
A Sallen-Key configuration gives us 2-pole filter using a single stage. Does there also exist some other configuration similar to Sallen-Key which give 3-pole or n-pole filter using a single stage?

Best wishes
PG
 

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