I don't know what to tell you. You went and changed the basic connections of the FFs. Why?

Change the circuit back to the configuration that was outputting 0 -> 1 -> 3 -> 2.

Then swap the two signals going to the display so that it is outputting 0 -> 2 -> 3 -> 1, which was the goal.

Get that done and then we can proceed.

 

I don't know what to tell you. You went and changed the basic connections of the FFs. Why?

Change the circuit back to the configuration that was outputting 0 -> 1 -> 3 -> 2.

Then swap the two signals going to the display so that it is outputting 0 -> 2 -> 3 -> 1, which was the goal.

Get that done and then we can proceed.

Please watch the video.


I did not understand the connection you said about the display.

PROTEUS installation on your computer?
what version if installed?

I can send the simulation files if you want.


0 -> 1 -> 3 -> 2 unchanged in setting.

 

Please watch the video.

One thing I didn't notice when I analyzed your circuit (Post #58) is that you are driving the D0 input of the display (the far right pin, which is the lsb) with the Qbar output of the left FF.

This is perfectly legitimate, but it means that you have to be very careful to track the impact of that when doing your design, which I doubt you have.

So that means that the output sequence displayed would be

State -> Displayed
00 -> 01
01 -> 00
10 -> 11
11 -> 10

State: 0 -> 2 -> 3
Display 1 -> 3 -> 2

The circuit shown will not enter State 01 (and if it did, it would get trapped there), so it is incapable of displaying 0 under normal operation.

I did not understand the connection you said about the display.

The display has 4 inputs with the most significant bit (msb) on the left and the least significant bit (lsb) on the right.

You will find your work to be much easier to follow if you order your FFs in the same order as the bits they represent. The left FF would then be the more significant and the right would be the less significant (of the two). That will aid greatly in communicating your design to your audience. Also, as mentioned before, label the schematic with the names used in your design work.

PROTEUS installation on your computer?
what version if installed?

I can send the simulation files if you want.

I don't have PROTEUS installed and I'm not going to install it.

0 -> 1 -> 3 -> 2 unchanged in setting.

That is not possible for the circuit shown in your Post #58: https://forum.allaboutcircuits.com/threads/flip-flop-counter-design.168596/post-1497121

So you must not be using that circuit. Please provide the schematic for the circuit that produced that sequence.

Looking at your video, I can see that it is, in fact, NOT that circuit (or any other circuit you've posted).

I am not a mind reader or remote viewer. We can't stay on the same page unless you post the circuit you are using.

Analyzing the circuit in the video, the state sequence is 0->2->3->1 and the values on the display should be 1->3->2->0, which if you look carefully, is exactly what they are. The first value displayed when you start the simulation is NOT 0, it is 1.

Why did you change the circuit you had in Post #54 (https://forum.allaboutcircuits.com/threads/flip-flop-counter-design.168596/post-1497108)?

All that needed to be done with that was to use swap the signals going to the display because you wired the right FF to the lsb even though the left FF is the lsb.

It seems like, since that point, you have been making more or less random changes to your circuit hoping that, at some point, something good "happens". Design-by-happening is not what you want to be aiming for.

Since I don't support "happenings", please either go back to the circuit in Post #54 and fix the connections to the display (since you have your work showing that design), or show the schematic for whatever different circuit you want to use, but show the design work that supports that circuit.

 

That looks fine. So now we have something that goes

0 -> 1 -> 3 -> 2

The next step is to shift the inputs to the display one position to the left (and ground the lsb input). What is the resulting output sequence? What is the relationship, mathematically, between the sequence above and the new sequence?

 

That looks fine. So now we have something that goes

0 -> 1 -> 3 -> 2

The next step is to shift the inputs to the display one position to the left (and ground the lsb input). What is the resulting output sequence? What is the relationship, mathematically, between the sequence above and the new sequence?

This is yet to be evident to the TS.
I would have left it as 4-bit BCD since this is what is required by the BCD-to-7-segment decoder/driver.

D C B A
0 0 0 0
0 1 1 0
0 1 0 0
0 0 1 0

Let the TS go through the exercise of designing a FSM with four flip-flops and then recognizing that two flip-flops are always 0.

 

This is yet to be evident to the TS.

The hope is that by taking the current design that he has working and making the five second modification requested and then being asked to observe and describe the relationship between two sequences that it will become evident. Notice that he's not being asked to predict the result, only observe and comment on it.

 

It is taking forever for the TS to recognize that only two flip-flops are required for a 4-state machine.
One possible reason could be a language issue and TS does not understand the meaning of state.

D C B A
0 0 0 0
0 1 1 0
0 1 0 0
0 0 1 0

 

The discussion that the TS and I are having isn't focused on how many flip flops are needed to represent a certain number of states. It is more fundamental than that in ensuring that he can design a machine to walk through an arbitrary trajectory through its state space. Having said that, I'm not really seeing anything recent that indicates that he doesn't understand that two flip flops give you access to four states, but it isn't evident yet to him that those states can mean anything we want them to mean. That is the rock that the current request is aimed at tipping over.

 

Not that it is important in this exercise but did the TS ever see the connection between the sequence 0-1-2-3
and his problem 0-6-4-2?

 

Not that it is important in this exercise but did the TS ever see the connection between the sequence 0-1-2-3
and his problem 0-6-4-2?

I don't know. That's what the current request should reveal to him.

 

Not that it is important in this exercise but did the TS ever see the connection between the sequence 0-1-2-3
and his problem 0-6-4-2?

How do we counting the numbers 6 and 4 with 2 ff?

 

How do we counting the numbers 6 and 4 with 2 ff?

Look at it again.

D C B A
0 0 0 0
0 1 1 0
0 1 0 0
0 0 1 0

 

Look at it again.

D C B A
0 0 0 0
0 1 1 0
0 1 0 0
0 0 1 0

D C B A
0 0 0 0 0
0 1 1 0. 6
0 1 0 0. 4
0 0 1 0. 2

Ok I understood the logic table, what exactly should I do now?

 

How do we counting the numbers 6 and 4 with 2 ff?

You are SO close to answering that question for yourself.

Just DO what I've requested several times already.

Take the circuit you currently have: https://forum.allaboutcircuits.com/search/

that goes through the sequence: 0 -> 1 -> 3 -> 2

and move the two signals going to the display one place to the left:


and report on the resulting sequence that is displayed.

Why won't you do that?

 

Look at the table again.

Which columns are changing?
Which columns are not changing?

D C B A
0 0 0 0
0 1 1 0
0 1 0 0
0 0 1 0

 

There's no trick, is there?

Of course, there is a trick. In this approach the count is limited to even numbers because the "1" binary digit is suppressed (grounded).

 

Of course, there is a trick. In this approach the count is limited to even numbers because the "1" binary digit is suppressed (grounded).

how should I do?

 

So what's the logic of this for odd numbers, 7 5 3?

 

So what's the logic of this for odd numbers, 7 5 3?

753
-642
------
111

 

753
-642
------
111

Does this work have a logic and algorithm formula?