Flashing several chips using an FT2232H chip

Thread Starter

doragasu

Joined Aug 2, 2017
5
Short story: I need documentation about how FT2232H based programmers for Lattice CPLDs/FPGAs wire the FT2232H signals.
Long story: read below.

I am designing a system containing:
  • An ATtiny;
  • A Lattice MachXO CPLD; and
  • An STM32 MCU.
Don't ask why this weird combination, let's say it is necessary and continue moving forward.

I want the end user to be able to easily program these 3 elements, so I am integrating an FT2232H chip on the PCB for this task. In addition to programing these 3 chips, I want to use the FT2232H for the STM32 to talk with the host PC (using SPI).

Currently I have managed to program all these items one by one using an FT2232H board:
  • The ATtiny using avrdude.
  • The CPLD using Lattice programmer.
  • The STM32 using OpenOCD (SWD interface).
But my problem is how to wire all these items together to be able to program them all without having to alter PCB connections. I was thinking in using the following strategy:
  • Use A bus to program the 3 chips.
  • Use B bus to communicate STM32 with PC (this way I can debug using bus A while PC and STM32 communicate).
For the A bus I was planning to connect everything as follows:
  1. Wire TCK/SCK, TDI/MOSI and TDO/MISO together to the corresponding pins of the 3 elements to program.
  2. Map a different TMS/CS pin for each of the 3 elements (a TMS pin for the CPLD, a CS pin for the Attiny connected to the chip reset, and another pin as the enable signal for the SWD interface tristate buffers).
  3. Use each corresponding software to make sure all unused TMS/CS pins are deactivated.
The unused TMS/CS deactivation should be as follows:
  1. When programming the CPLD, use TMS, and ensure that CS keeps the AVR in reset, and the SWD enable disconnects the buffers.
  2. When programming the AVR, make sure TMS disables CPLD JTAG interface, and SWD buffers for STM32 are high Z.
  3. When programming the STM32, keep the AVR in reset and the CPLD JTAG disabled.
I think using openocd and avrdude I can map pins to achieve points 2 and 3 above (they allow writing configuration files with pretty flexible pin definitions). But unfortunately I do not know how signals are mapped to the FT2232 when using the Lattice Programmer, so I don't know if I can manage to accomplish point 1 above.

Does this approach make sense?
Does anyone have information about lattice programmer signals (other than the typical TCK, TDI, TDO & TMS) and how they are mapped to the FT2232?

BTW, other option I might try is using an FT4232 instead of an FT2232, but I would like to try with the FT2232 first.
 

Thread Starter

doragasu

Joined Aug 2, 2017
5
I think that just from the description, the setup might be difficult to understand, so I have drawn a quick diagram:


Hope it helps to depict the intended setup!
 

DickCappels

Joined Aug 21, 2008
10,152
Are you using this approach rather than the more obvious one of having the STM32 program the other two chips because you already have software that uses the FTDI interface?
 

Thread Starter

doragasu

Joined Aug 2, 2017
5
Yes, that's it. Currently I have software that can accomplish the programming of these 3 chips using an FT2232H.

If I could program the CPLD/FPGA and the ATtiny using the STM32 directly, that could be way better, and the design would be more simple. But I do not know if there is software available both for the STM32 and the PC client side for these tasks. I suspect there might be something for the ATtiny, but it might not be possible for the CPLD/FPGA, because as far as I know, the protocol used to upload bitfiles on the MachXO chips has not been disclosed.
 

DickCappels

Joined Aug 21, 2008
10,152
I wish I knew the protocol for the other chips. I can tell you that to program and ATTINY device using in-system programming you need to hold the RESET pin low. Have you seen

Are you aware of PonyProg? http://www.lancos.com/prog.htm
Of course you can just go toward the end of the datasheet for your ATTINY device and follow the chip programming instructions.
 

Thread Starter

doragasu

Joined Aug 2, 2017
5
You are right about holding RESET low, I already knew. There is a mistake in my diagram, inside the ATtiny box, the CS pin should be RESET pin.

I could take the challenge of implement the programming protocol myself for the ATtiny. But I still would have a problem about the lack of documentation for the Lattice CPLD.
 

DickCappels

Joined Aug 21, 2008
10,152
It sounds like you are stuck with using the FTDI part. The reason I mentioned PonyProg is because it might be of use to you for programming the ATTINY if you don't already have the software.
 

Thread Starter

doragasu

Joined Aug 2, 2017
5
Following my initial design attempt above looked risky, so I decided changing the route: I will use a 2-port USB hub to connect the FT2232 on one downstream port and the STM on the other. This way the FT2232 can easily program the AVR and the FPGA, while the STM can be programmed using the USB bootloader. I loose the ability to debug STM code using OpenOCD, but the code is simple enough to survive without it, and the interface is greatly simplified.
 
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