Hello there.

I'm relatively new to (digital) circuits, so I search an IC with the following truth table best in the 74xx line:

In In In In Out
0  0  0  0  x (maybe Z)
1  x  x  x  a
0  1  x  x  b
0  0  1  x  c
0  0  0  1  d

Where 1 coult be 0 and vice versa, x = don't cares, Z = high impedance and a != b != c != d.

I'll create a priority system. When the first component "activate" the line, the circuit should do something, no matter the other components. When the second compontent activate the line and the first don't do it, the circuit should do something other, no matter component 2 and 3 do it.

I won't build this using simple logic gates, because this get big.


Thank you

 

How about 74147 or 74148? Just searching for a priority encoder and 7400 series

What do you need this for? Maybe getting some programable logic device might be a better idea.

 

Thank you
I wan't try design a shared bus. When the bus is free and any component want to send, the component with the highest priority get the permission to send.

 

Using 74147 or 74148 and CD4051.
147,148 are the decoder for highest priority to get the permission, and to choose the cd4051 to open the gate to get the data from d0 to d7.

 

Why the CD4051?
I through about D-Flipflops with Tristate output, e. g. the 74173. When the component get the permission, it will send the adress of the target component and the data on a edge of the bus clock. The target component read the data from the bus on the opposite clock edge (Send on the rising and read on the falling or send on the falling and read on the rising). The reading component prepare the answer and request a send. (Or maybe store the incoming data on a Last-in-last-out-queue etc. if he has no time to answer or must answer to another request first.)

But it think i'm thinking to complex. ^^
Here I would need many things. 1 data line for send request, 1 for send permission, 1 for the bus clock, 3 for 8 possible target components, the shared data lines self and a LILO-Queue on each component, because 2 or more higher priority components could send to the same target before it could send a answer or handle a request.

Thank you

 

Hello there.

I'm relatively new to (digital) circuits, so I search an IC with the following truth table best in the 74xx line:

In In In In Out
0  0  0  0  x (maybe Z)
1  x  x  x  a
0  1  x  x  b
0  0  1  x  c
0  0  0  1  d

Where 1 coult be 0 and vice versa, x = don't cares, Z = high impedance and a != b != c != d.

I'll create a priority system. When the first component "activate" the line, the circuit should do something, no matter the other components. When the second compontent activate the line and the first don't do it, the circuit should do something other, no matter component 2 and 3 do it.

I won't build this using simple logic gates, because this get big.


Thank you

A field programmable ROM would take just one.

 

What do a, b, c, d represent in your truth table?
What is (!)?

 

Your "priority" need makes it sound like a quiz circuit (e.g., http://www.zen22142.zen.co.uk/Circuits/Misc/quiz.htm). Is your question whether we can find a single chip to do that?

John

 

He means actual priority, such that when devices A and B request bus at the same time, the one with higher priority will be granted bus arbitration.
Another possibility to do the arbitration with minimal parats count would be along the ways CAN works, that is open collector bus. The device with lowest address will win arbitration, as it will pull all the arbitration lines low. All other devices will sense that the bus contains a different address than their own and will back off and wait.

 

Why the CD4051?
I through about D-Flipflops with Tristate output, e. g. the 74173. When the component get the permission, it will send the adress of the target component and the data on a edge of the bus clock. The target component read the data from the bus on the opposite clock edge (Send on the rising and read on the falling or send on the falling and read on the rising). The reading component prepare the answer and request a send. (Or maybe store the incoming data on a Last-in-last-out-queue etc. if he has no time to answer or must answer to another request first.)

But it think i'm thinking to complex. ^^
Here I would need many things. 1 data line for send request, 1 for send permission, 1 for the bus clock, 3 for 8 possible target components, the shared data lines self and a LILO-Queue on each component, because 2 or more higher priority components could send to the same target before it could send a answer or handle a request.

Thank you

The CD4051 offering the easy way to get the input data from 1 of 8, if you have to using the data and clock and have a sequence then maybe you need to use the 74LS173 or you can attach your circuit and labeling the input and output infos.

 

ok, thank you