Error in Laser Driver Circuit simulation

Thread Starter

nirbec89

Joined Feb 25, 2021
14
Hi,
I'm trying to build a DIY simple laser driver with DAC 0-3.3V gain control over the LD, with modulation from Function generator.
In LTSpice everything seems to work OK, but when I built the PCB in real life I ran into unexpected behaviors that honestly didn't succeeded to analyze.

Could you please look in the schematics and try to identify what's wrong?

Simulation graph images shows current flows through the LD, which in simulation is indeed acting as expected

Thank you!
 

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Thread Starter

nirbec89

Joined Feb 25, 2021
14
Hi,
Attached in the original post and also here in the answer.

I provide the 7V voltage from one power supply, and 0-3.3v from another power supply.
First I can see the 0-3.3v power supply immediately have 7V on the screen even thought his potentiometer is on '0', and current shown is -17 mA.

Anyway i tried to increase the voltage and it didn't have any effect.

Generally speaking it should support ~ 0-200mA and around 10khz freq

Thank you!
 

ericgibbs

Joined Jan 29, 2010
12,269
hi 89,
LTS is reporting an error with your TIP120 model, so I have used mine.

What have you set V5 Source to?
All the V sources are set to DC on the asc file you posted.

E
 

Thread Starter

nirbec89

Joined Feb 25, 2021
14
hi 89,
LTS is reporting an error with your TIP120 model, so I have used mine.

What have you set V5 Source to?
All the V sources are set to DC on the asc file you posted.

E
Hi,
You are right, sorry.
Attached is a fixed .asc with pulse dc sources.

V5 supposed to be enable/disable for the whole driver,
So only when V5 is '0' volt the LD could work.
 

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Thread Starter

nirbec89

Joined Feb 25, 2021
14
Thank you Eric,
Your simulation is slightly different, I assume its related to the different TIP120 models.
Attached is also a image of V(N002) DC sweep between 0-3.3V and CW operation , you can see the current over the LD is increasing nice and linear as expected.

In my real test the LD have around 50mA current flowing even thought V3 is '0' voltage, when I'm increasing V3 voltage there is no influence on the LD current at all.

Also more weird thing is I'm using two power supply, one is 7V for the LD, OpAmp and Function Generator simulation (currently 7V supply CW to simulate 100% Duty Cycle).
and the second power supply is 0-3.3v for the ADC V3 input.

When I'm applying the 7V on the power supply , the second power supply (V3) screen shows 7V even thought he is pointed to 0V as start .

Basically I thought you will recognize some issue in my schematic, but if it looks OK and you can't spot any issues maybe its related to my physical wiring/wrong connections..
 

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Thread Starter

nirbec89

Joined Feb 25, 2021
14
hi 89,
Is this what you are requiring.
Note the 68pF across R7 on the final OPA.
E
This configuration looks much better on simulation.
Do you think the missing capacitor can explain the issues I ran into in physical test?
(just posted an reply with the behaviour)
 

ericgibbs

Joined Jan 29, 2010
12,269
hi,
With V3=0V, there is still a signal into U3 OPA NI input.
Its via the Base to Emitter diode of Q5, its about 3mV amplitude and appears a 2.3V to 3.3V signal on the TIP Base, so there will be steady LD current.
E

Update:
What is the purpose of Q3.??
 

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Thread Starter

nirbec89

Joined Feb 25, 2021
14
hi,
With V3=0V, there is still a signal into U3 OPA NI input.
Its via the Base to Emitter diode of Q5, its about 3mV amplitude and appears a 2.3V to 3.3V signal on the TIP Base, so there will be steady LD current.
E

Update:
What is the purpose of Q3.??
Small LD current as you described is OK while the circuit in standby mode (0v).
Q3 supposed to be current limiter depends on the voltage drop over R1 that can be changed to potentiometer in order to modify the current limit.

In this case that you can't find any major problem and the simulation works, it might be that i have faulty component or bad connection on my physical test circuit.
 

ericgibbs

Joined Jan 29, 2010
12,269
hi,
Drawing current thru R3 will not pull down the voltage of V1 in simulation, it is an ideal voltage source, ie: no internal resistance.

E
 

Thread Starter

nirbec89

Joined Feb 25, 2021
14
Eric, Bordodynov,
Thank you very much for your help and optimization tips, its indeed looks better.

Also the physical circuit is working , I had one faulty BJT.
Once i replaced it, the circuit working exact according to the simulation.

Thank you!
 

Thread Starter

nirbec89

Joined Feb 25, 2021
14
Hi Again,
I manufactured the board as we optimized it.
And I'll be happy to some help debugging as I'm bit struggling .

The BJT(Q5) from last example ran into saturation since his base is toggling between 0 to 3.3v,
and the collector is ranging from 0 to 3.3v

while the collector voltage is lower than the base, the BJT is going to saturation and seems like I'm getting some back voltage/current at the collector, so changing the collector voltage not making change. (is it reasonable?) maybe i'm misunderstood something?

To solve it i design a version with MOSFET instead , and to fully 'open' it i used opamp , I'm still get switching noises at the simulation.
If its not fully opened i'm saturating at some point so i'm not using the 0-3.3v analog range.

Is it better solution from the BJT? is opamp to gain the logic level is good option?

One more modification i did is to raise the load voltage to 12V in order to support laser diodes with higher forward voltage.
The opamp remains at 7V for now since it seems that the MCP602 has maximum 7V input.

Thank you!
Nir.
 

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Thread Starter

nirbec89

Joined Feb 25, 2021
14
Attached the requested files,

Generally speaking the circuit works flawless except the switching section we are talking about..
I prefer to stay with the BJT solution finalized last time if its works in real life..
Please advise

With the BJT in the previous schematic we talked about last time,
since the collector voltage is less than the base, the BJT(Q5) acts in saturation. I saw in the power supply negative current since its flowing from base to collector, and raising the voltage didn't had any effect until certain point it got out from saturation,
so in this case i'm losing the 0-3.3v analog gain(V3)
 

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